📄 suma.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity suma is
port
(
k,m : in std_logic_vector (3 downto 0);
x : buffer std_logic_vector(4 downto 0);
s : out std_logic_vector (13 downto 0)
);
end suma;
architecture pract of suma is
begin
x <= ('0'& k) + ('0'& m);
-- abcdefg
-- 01234567...13
s <= "11111101111110" when (x = "00000") else
"11111100110000" when (x = "00001") else
"11111101101101" when (x = "00010") else
"11111101111001" when (x = "00011") else
"11111100110011" when (x = "00100") else
"11111101011011" when (x = "00101") else
"11111101011111" when (x = "00110") else
"11111101110001" when (x = "00111") else
"11111101111111" when (x = "01000") else
"11111101111011" when (x = "01001") else
"01100001111110" when (x = "01010") else
"01100000110000" when (x = "01011") else
"01100001101101" when (x = "01100") else
"01100001111001" when (x = "01101") else
"01100000110011" when (x = "01110") else
"01100001011011" when (x = "01111") else
"01100001011111" when (x = "10000") else
"01100001110001" when (x = "10001") else
"01100001111111" when (x = "10010") else
"01100001111011" when (x = "10011") else
"11011011111110" when (x = "10100") else
"11011010110000" when (x = "10101") else
"11011011101101" when (x = "10110") else
"11011011111001" when (x = "10111") else
"11011010110011" when (x = "11000") else
"11011011011011" when (x = "11001") else
"11011011011111" when (x = "11010") else
"11011011110001" when (x = "11011") else
"11011011111111" when (x = "11100") else
"11011011111011" when (x = "11101") else
"11110011111110" when (x = "11110") else
"XXXXXXXXXXXXXX";
end pract;
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