_primary.vhd

基于VHDL（verilog）语言的UART的设计与实现。全面模仿AVR的UART功能

library verilog;
use verilog.vl_types.all;
entity top is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        ad              : inout  vl_logic_vector(7 downto 0);
        addr            : in     vl_logic_vector(7 downto 0);
        wr_n            : in     vl_logic;
        rd_n            : in     vl_logic;
        ale             : in     vl_logic;
        txd             : out    vl_logic;
        rxd             : in     vl_logic;
        int_o           : out    vl_logic;
        uart_clk        : out    vl_logic
    );
end top;