main.vt

FPGA与dSP的接口

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "05/08/2008 22:28:42"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    main
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module main_vlg_vec_tst();
// constants                                           
// general purpose registers
reg ce;
reg clk;
reg [17:0] din;
reg [15:0] treg_ed;
reg oe;
reg re;
reg we;
// wires                                               
wire ardy;
wire [17:0] dout;
wire [15:0] ed;
wire error;
wire int;

// assign statements (if any)                          
assign ed = treg_ed;
main i1 (
// port map - connection between master ports and signals/registers   
	.ardy(ardy),
	.ce(ce),
	.clk(clk),
	.din(din),
	.dout(dout),
	.ed(ed),
	.error(error),
	.\int (int),
	.oe(oe),
	.re(re),
	.we(we)
);
initial 
begin 
#1000000 $stop;
end 

// clk
always
begin
	clk = 1'b0;
	clk = #5000 1'b1;
	#5000;
end 

// oe
initial
begin
	oe = 1'b1;
	oe = #130000 1'b0;
	oe = #210000 1'b1;
end 

// re
initial
begin
	re = 1'b1;
	re = #130000 1'b0;
	re = #210000 1'b1;
end 

// we
initial
begin
	we = 1'b1;
	we = #520000 1'b0;
	we = #200000 1'b1;
end 

// ce
initial
begin
	ce = 1'b1;
	ce = #130000 1'b0;
	ce = #210000 1'b1;
	ce = #180000 1'b0;
	ce = #200000 1'b1;
end 
// din[ 17 ]
initial
begin
	din[17] = 1'b0;
	din[17] = #180000 1'bZ;
end 
// din[ 16 ]
initial
begin
	din[16] = 1'b0;
	din[16] = #180000 1'bZ;
end 
// din[ 15 ]
initial
begin
	din[15] = 1'b0;
	din[15] = #180000 1'bZ;
end 
// din[ 14 ]
initial
begin
	din[14] = 1'b0;
	din[14] = #180000 1'bZ;
end 
// din[ 13 ]
initial
begin
	din[13] = 1'b0;
	din[13] = #180000 1'bZ;
end 
// din[ 12 ]
initial
begin
	din[12] = 1'b0;
	din[12] = #180000 1'bZ;
end 
// din[ 11 ]
initial
begin
	din[11] = 1'b0;
	din[11] = #180000 1'bZ;
end 
// din[ 10 ]
initial
begin
	din[10] = 1'b0;
	din[10] = #180000 1'bZ;
end 
// din[ 9 ]
initial
begin
	din[9] = 1'b0;
	din[9] = #180000 1'bZ;
end 
// din[ 8 ]
initial
begin
	din[8] = 1'b0;
	din[8] = #180000 1'bZ;
end 
// din[ 7 ]
initial
begin
	din[7] = 1'b0;
	din[7] = #180000 1'bZ;
end 
// din[ 6 ]
initial
begin
	din[6] = 1'b0;
	din[6] = #180000 1'bZ;
end 
// din[ 5 ]
initial
begin
	din[5] = 1'b0;
	din[5] = #180000 1'bZ;
end 
// din[ 4 ]
initial
begin
	din[4] = 1'b0;
	din[4] = #160000 1'b1;
	din[4] = #20000 1'bZ;
end 
// din[ 3 ]
initial
begin
	din[3] = 1'b0;
	din[3] = #80000 1'b1;
	din[3] = #80000 1'b0;
	din[3] = #20000 1'bZ;
end 
// din[ 2 ]
initial
begin
	repeat(2)
	begin
		din[2] = 1'b0;
		din[2] = #40000 1'b1;
		# 40000;
	end
	din[2] = 1'b0;
	din[2] = #20000 1'bZ;
end 
// din[ 1 ]
initial
begin
	repeat(4)
	begin
		din[1] = 1'b0;
		din[1] = #20000 1'b1;
		# 20000;
	end
	din[1] = 1'b0;
	din[1] = #20000 1'bZ;
end 
// din[ 0 ]
initial
begin
	repeat(9)
	begin
		din[0] = 1'b0;
		din[0] = #10000 1'b1;
		# 10000;
	end
	din[0] = 1'bZ;
end 
// ed[ 15 ]
initial
begin
	treg_ed[15] = 1'bZ;
	treg_ed[15] = #510000 1'b0;
	treg_ed[15] = #220000 1'bZ;
end 
// ed[ 14 ]
initial
begin
	treg_ed[14] = 1'bZ;
	treg_ed[14] = #510000 1'b0;
	treg_ed[14] = #220000 1'bZ;
end 
// ed[ 13 ]
initial
begin
	treg_ed[13] = 1'bZ;
	treg_ed[13] = #510000 1'b0;
	treg_ed[13] = #220000 1'bZ;
end 
// ed[ 12 ]
initial
begin
	treg_ed[12] = 1'bZ;
	treg_ed[12] = #510000 1'b0;
	treg_ed[12] = #220000 1'bZ;
end 
// ed[ 11 ]
initial
begin
	treg_ed[11] = 1'bZ;
	treg_ed[11] = #510000 1'b0;
	treg_ed[11] = #220000 1'bZ;
end 
// ed[ 10 ]
initial
begin
	treg_ed[10] = 1'bZ;
	treg_ed[10] = #510000 1'b0;
	treg_ed[10] = #220000 1'bZ;
end 
// ed[ 9 ]
initial
begin
	treg_ed[9] = 1'bZ;
	treg_ed[9] = #510000 1'b0;
	treg_ed[9] = #220000 1'bZ;
end 
// ed[ 8 ]
initial
begin
	treg_ed[8] = 1'bZ;
	treg_ed[8] = #510000 1'b0;
	treg_ed[8] = #220000 1'bZ;
end 
// ed[ 7 ]
initial
begin
	treg_ed[7] = 1'bZ;
	treg_ed[7] = #510000 1'b0;
	treg_ed[7] = #220000 1'bZ;
end 
// ed[ 6 ]
initial
begin
	treg_ed[6] = 1'bZ;
	treg_ed[6] = #510000 1'b0;
	treg_ed[6] = #220000 1'bZ;
end 
// ed[ 5 ]
initial
begin
	treg_ed[5] = 1'bZ;
	treg_ed[5] = #510000 1'b0;
	treg_ed[5] = #220000 1'bZ;
end 
// ed[ 4 ]
initial
begin
	treg_ed[4] = 1'bZ;
	treg_ed[4] = #510000 1'b0;
	treg_ed[4] = #160000 1'b1;
	treg_ed[4] = #60000 1'bZ;
end 
// ed[ 3 ]
initial
begin
	treg_ed[3] = 1'bZ;
	treg_ed[3] = #510000 1'b0;
	treg_ed[3] = #80000 1'b1;
	treg_ed[3] = #80000 1'b0;
	treg_ed[3] = #60000 1'bZ;
end 
// ed[ 2 ]
initial
begin
	treg_ed[2] = 1'bZ;
	# 510000;
	repeat(2)
	begin
		treg_ed[2] = 1'b0;
		treg_ed[2] = #40000 1'b1;
		# 40000;
	end
	treg_ed[2] = 1'b0;
	treg_ed[2] = #40000 1'b1;
	treg_ed[2] = #20000 1'bZ;
end 
// ed[ 1 ]
initial
begin
	treg_ed[1] = 1'bZ;
	# 510000;
	repeat(5)
	begin
		treg_ed[1] = 1'b0;
		treg_ed[1] = #20000 1'b1;
		# 20000;
	end
	treg_ed[1] = 1'b0;
	treg_ed[1] = #20000 1'bZ;
end 
// ed[ 0 ]
initial
begin
	treg_ed[0] = 1'bZ;
	# 510000;
	repeat(11)
	begin
		treg_ed[0] = 1'b0;
		treg_ed[0] = #10000 1'b1;
		# 10000;
	end
	treg_ed[0] = 1'bZ;
end 
initial 
begin 
#1000000 $stop;
end 
endmodule