decode.v

来自「FPGA与dSP的接口」· Verilog 代码 · 共 34 行

module decode(
   input en,clk,half_full,
   input [17:0] datain,
   output reg [15:0] dataout,
   output reg r_wrreq,data_error,
   output reg ack);

integer n;
reg error=0;
//奇偶校验
always @ (posedge clk)
   if(en==1) 
      begin
          for(n=0;n<17;n=n+1) error=datain[n]+error;
          data_error=error;
      end
    else data_error=1;
//接收方写请求
always @ (posedge clk) 
   if(en==1) r_wrreq=datain[15];
   else r_wrreq=0;
//发送握手信号
always @ (posedge clk) 
   if(en==1) 
   begin
      if (half_full==1) ack=0;
      else ack=1;
   end
   else ack=0;
 //数据
always @ (posedge clk)
   if(en==1) dataout[15:0]=datain[15:0];
   else dataout=0;
endmodule