dsp_port.v

来自「FPGA与dSP的接口」· Verilog 代码 · 共 43 行

module dsp_port(
   input clk,
   input ce,
   input oe,
   input we,
   input re,
   input [15:0] din,
   input wr_ready,
   input rd_ready,
   input rdreq,
   
   output reg ardy,
   output reg int,
   output reg rclk,
   output reg wclk,
   output reg ren,
   output reg wen,
   output [15:0] dout,
   
   inout [15:0] ed
);

always @ (posedge clk) 
   if(ce==0) 
   begin
      rclk=~re;
      wclk=~we;
      ren=~oe;
      wen=oe;
  end
//双向数据口，不能写在always句子中
assign   ed=((ce==0)&&(oe==0))?din:16'hZZZZ;
assign   dout=((ce==0)&&(oe==1))?ed:16'hZZZZ;

always @ (posedge clk)
   if((ce==0)&&(oe==0)) ardy=rd_ready;
   else if((ce==0)&&(oe==1)) ardy=wr_ready;
   else ardy=1'bZ;

always @ (posedge clk)
   if(rdreq==1) int=0;
   else int=1;
endmodule