dsp_port_tb.v

来自「FPGA与dSP的接口」· Verilog 代码 · 共 53 行

module dsp_port_tb;
   reg clk;
   reg ce;
   reg oe;
   reg we;
   reg re;
   reg [15:0] din;
   reg wr_ready;
   reg rd_ready;
   reg rdreq;
   wire ardy;
   wire int;
   wire wclk;
   wire rclk;
   wire ren;
   wire wen;
   wire [15:0] dout;
   wire [15:0] ed;
   
  dsp_port dut(.clk(clk),.ce(ce),.oe(oe),.we(we),.re(re),.din(din),.wr_ready(wr_ready),.rd_ready(rd_ready),.ardy(ardy),.int(int),.rclk(rclk),.wclk(wclk),.dout(dout),.ed(ed),.rdreq(rdreq));
  
   initial begin
       clk=0;
       forever begin
           #10 clk=~clk;
       end
   end
   
   always @ (negedge re) din=$random;
   assign ed=(ce==0&&oe==1)?$random:16'hzzzz;
   
   initial begin
       #20
       ce=1;
       oe=1;
       we=1;
       re=1;
       wr_ready=1;
       rd_ready=1;
       rdreq=0;
       #5
       rdreq=1;
       #10
       ce=0;
       oe=0;
       re=0;
       #50
       rdreq=0;
       oe=1;
       #10
       we=0;
   end
endmodule