main.v

FPGA与dSP的接口

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module main(
	clk,
	ce,
	oe,
	we,
	re,
	din,
	ardy,
	int,
	error,
	dout,
	ed
);

input	clk;
input	ce;
input	oe;
input	we;
input	re;
input	[17:0] din;
output	ardy;
output	int;
output	error;
output	[17:0] dout;
inout	[15:0] ed;

wire	[3:0] full;
wire	negclk;
wire	rdrdy;
wire	wrdy;
wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	[15:0] SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_7;
wire	[15:0] SYNTHESIZED_WIRE_8;
wire	SYNTHESIZED_WIRE_9;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;
wire	[15:0] SYNTHESIZED_WIRE_12;
wire	[15:0] SYNTHESIZED_WIRE_13;

assign	SYNTHESIZED_WIRE_0 = 1;
assign	SYNTHESIZED_WIRE_1 = 1;




decode	b2v_inst(.en(SYNTHESIZED_WIRE_0),
.clk(clk),.half_full(full[3]),.datain(din),.r_wrreq(SYNTHESIZED_WIRE_5),.data_error(error),.ack(SYNTHESIZED_WIRE_2),.dataout(SYNTHESIZED_WIRE_8));

encode	b2v_inst1(.en(SYNTHESIZED_WIRE_1),
.clk(negclk),.ack(SYNTHESIZED_WIRE_2),.s_empty(SYNTHESIZED_WIRE_3),.datain(SYNTHESIZED_WIRE_4),.s_rdreq(SYNTHESIZED_WIRE_11),.dataout(dout));

r_fifo	b2v_inst2(.wrreq(SYNTHESIZED_WIRE_5),
.wrclk(negclk),.rdreq(SYNTHESIZED_WIRE_6),.rdclk(SYNTHESIZED_WIRE_7),.data(SYNTHESIZED_WIRE_8),.rdempty(rdrdy),.q(SYNTHESIZED_WIRE_13),.wrusedw(full));

s_fifo	b2v_inst3(.wrreq(SYNTHESIZED_WIRE_9),
.wrclk(SYNTHESIZED_WIRE_10),.rdreq(SYNTHESIZED_WIRE_11),.rdclk(clk),.data(SYNTHESIZED_WIRE_12),.wrfull(wrdy),.rdempty(SYNTHESIZED_WIRE_3),.q(SYNTHESIZED_WIRE_4));

dsp_port	b2v_inst4(.clk(negclk),
.ce(ce),.oe(oe),.we(we),.re(re),.wr_ready(wrdy),.rd_ready(rdrdy),.rdreq(full[2]),.din(SYNTHESIZED_WIRE_13),.ed(ed),.ardy(ardy),.int(int),.rclk(SYNTHESIZED_WIRE_7),.wclk(SYNTHESIZED_WIRE_10),.ren(SYNTHESIZED_WIRE_6),.wen(SYNTHESIZED_WIRE_9),.dout(SYNTHESIZED_WIRE_12));
assign	negclk =  ~clk;


endmodule