main_tb.v

来自「FPGA与dSP的接口」· Verilog 代码 · 共 40 行

module main_tb;
   reg	clk;
   reg	ce;
   reg	oe;
   reg	we;
   reg	re;
   reg	[17:0] din;
   wire	ardy;
   wire	int;
   wire	error;
   wire	[17:0] dout;
   wire	[15:0] ed;
   main dut(.clk(clk),.ce(ce),.oe(oe),.we(we),.re(re),.din(din),.ardy(ardy),.int(int),.error(error),.dout(dout),.ed(ed));
   
   initial begin
       clk=0;
       forever begin
           #10 clk=~clk;
       end
   end
   
   always @ (negedge clk) din=$random;
   assign ed=(ce==0&&oe==1)?$random:16'hzzzz;
   
   always @(negedge int) 
      begin
         ce=0;
         oe=0;
         we=1;
         re=0;
      end
   always @(posedge int)
      begin
         ce=0;
         oe=1;
         we=0;
         re=1;
      end   
   
endmodule