encode_tb.v

来自「FPGA与dSP的接口」· Verilog 代码 · 共 40 行

module encode_tb;
    reg en,clk,ack,s_empty;
    reg [15:0] datain;
    wire [17:0] dataout;
    wire s_rdreq;
    encode dut(.en(en),.clk(clk),.ack(ack),.s_empty(s_empty),.datain(datain),.dataout(dataout),.s_rdreq(s_rdreq));
    
    initial 
    begin
       clk=0;
       forever begin
           #5 clk=~clk;
       end
    end
    
    initial
    begin
        en=1;
        ack=0;
        s_empty=1;
        #10
        ack=1;
        s_empty=0;
        #10
        ack=1;
        s_empty=1;
        #10 en=0;
        #15 en=1;
    end
    
    always @(negedge clk)
    datain=$random;
    
    initial
    begin
        repeat(20) $monitor("datain %b dataout %b",datain,dataout);
    end   
endmodule