share_input.v

来自「电梯控制程序！！ verilog 描述的」· Verilog 代码 · 共 51 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:15:41 01/13/07
// Design Name:    
// Module Name:    share_input
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module share_input(start_share1,address_user1,address_ok_share1,
                   start_share2,address_user2,address_ok_share2,
		             start_slect,address_user,address_ok_slect,address_user_h);

input start_slect,address_ok_slect;
input [3:0] address_user;
input [1:0]	address_user_h;
output start_share1,start_share2,address_ok_share1,address_ok_share2; 
output [3:0] address_user1,address_user2;
 
reg start_share1,start_share2,address_ok_share1,address_ok_share2;
reg [3:0] address_user1,address_user2;
 
always @ (address_user_h or address_user or start_slect or address_ok_slect)
begin
case (address_user_h)
0:begin	address_user2 = 15;address_user1 = address_user; start_share2='b1;start_share1=start_slect;
         address_ok_share2='b1; address_ok_share1=address_ok_slect;end

1:begin	address_user1 = 15;address_user2 = address_user; start_share1='b1;start_share2=start_slect;
         address_ok_share1='b1; address_ok_share2=address_ok_slect;end
2:begin	address_user2 = 15;address_user1 = address_user; start_share2='b1;start_share1=start_slect;
         address_ok_share2='b1; address_ok_share1=address_ok_slect;end
3:begin	address_user2 = 15;address_user1 = address_user; start_share2='b1;start_share1=start_slect;
         address_ok_share2='b1; address_ok_share1=address_ok_slect;end
endcase
end


endmodule