cu_lift_1.v

电梯控制程序！！ verilog 描述的

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    21:55:23 01/11/07
// Design Name:    
// Module Name:    cu_lift_1
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module cu_lift_1(wait_in,free_in,up_in,state,des_floor,CLE,DESLE,cur_floor,des_cu_floor,des_user_floor,
               up_in_f,start,bye,reset,clk);
input [15:0] des_cu_floor,des_user_floor;
input [3:0] cur_floor;
input start,bye,up_in_f,reset,clk;

output wait_in,free_in,up_in,CLE,DESLE;
output [15:0] des_floor;
output [1:0]state;
reg wait_in,free_in,up_in,CLE,DESLE,stay_s1,stay_s0;

parameter S0 = 0,S1=1,S2=2,S3=3;
reg [1:0] state,next_state;
reg [3:0] start_j,start_i;
reg [15:0] des_floor;

assign or_des = {|des_floor};

always @ (negedge reset or posedge clk)
begin
if(!reset) 	 state <=S0;
else state <= next_state;
end


always @(state or des_floor or start or cur_floor or or_des or bye or start_j or start_i or reset)
begin
CLE = 0;	 //=1时开始计数
stay_s1 = 0;
stay_s0 = 0;
case(state)
S0:begin 
  if(start_i == 2 &&or_des==1) begin next_state  = S1;stay_s1 = 1;end 
    else   next_state  = S0;
   free_in = 1;wait_in = 1; up_in = up_f(cur_floor,des_floor,up_in_f,wait_in);end
S1:begin 
   if(start_j<10)  next_state  = S1;
	else 
   if(or_des==0)begin next_state  = S0;stay_s0 = 1; end
    else if(des_cu_is1(cur_floor,des_cu_floor)==1) next_state  = S2;
	    else if(des_cu_is1(cur_floor,des_user_floor)==1) next_state  = S3;
		 else next_state  = S1;
	wait_in = 0;up_in = up_f(cur_floor,des_floor,up_in_f,wait_in);free_in = 0;end
S2:begin 
   if(start == 0) begin next_state  = S1;stay_s1 = 1;end
    else next_state  = S2;
      wait_in = 1;free_in = 0;up_in = up_f(cur_floor,des_floor,up_in_f,wait_in);end
S3:begin
	if(bye==1) 
     begin if(or_des == 0)  begin next_state  = S0;stay_s0 = 1; end
	        else begin next_state  = S1;stay_s1 = 1;end end
	  else  next_state  = S3; 
     wait_in = 1;up_in = up_f(cur_floor,des_floor,up_in_f,wait_in);CLE = 1;free_in = 0;end
endcase
end

always @ (negedge reset or posedge clk)
begin
	if(!reset) des_floor = des_cu_floor | des_user_floor;
	else if (up_in==1&&free_in==0)
	 case(cur_floor)
	 0: des_floor = {des_cu_floor[15:1] | des_user_floor[15:1],1'b0};
    1: des_floor = {des_cu_floor[15:2] | des_user_floor[15:2],2'b0};
	 2: des_floor = {des_cu_floor[15:3] | des_user_floor[15:3],3'b0};
	 3: des_floor = {des_cu_floor[15:4] | des_user_floor[15:4],4'b0};
	 4: des_floor = {des_cu_floor[15:5] | des_user_floor[15:5],5'b0};
	 5: des_floor = {des_cu_floor[15:6] | des_user_floor[15:6],6'b0};
	 6: des_floor = {des_cu_floor[15:7] | des_user_floor[15:7],7'b0};
	 7: des_floor = {des_cu_floor[15:8] | des_user_floor[15:8],8'b0};
	 8: des_floor = {des_cu_floor[15:9] | des_user_floor[15:9],9'b0};
	 9: des_floor = {des_cu_floor[15:10] | des_user_floor[15:10],10'b0};
	 10:des_floor = {des_cu_floor[15:11] | des_user_floor[15:11],11'b0};
	 11:des_floor = {des_cu_floor[15:12] | des_user_floor[15:12],12'b0};
	 12:des_floor = {des_cu_floor[15:13] | des_user_floor[15:13],13'b0};
	 13:des_floor = {des_cu_floor[15:14] | des_user_floor[15:14],14'b0};
	 14:des_floor = {des_cu_floor[15] | des_user_floor[15],15'b0};
	 15:des_floor = 0;
	endcase

	else if(free_in==0)
	 case(cur_floor)
	 0: des_floor = 0;
    1: des_floor = {15'b0,des_cu_floor[0] | des_user_floor[0]};
	 2: des_floor = {13'b0,des_cu_floor[1:0] | des_user_floor[1:0]};
	 3: des_floor = {12'b0,des_cu_floor[2:0] | des_user_floor[2:0]};
	 4: des_floor = {11'b0,des_cu_floor[3:0] | des_user_floor[3:0]};
	 5: des_floor = {10'b0,des_cu_floor[4:0] | des_user_floor[4:0]};
	 6: des_floor = {9'b0,des_cu_floor[5:0] | des_user_floor[5:0]};
	 7: des_floor = {8'b0,des_cu_floor[6:0] | des_user_floor[6:0]};
	 8: des_floor = {7'b0,des_cu_floor[7:0] | des_user_floor[7:0]};
	 9: des_floor = {6'b0,des_cu_floor[8:0] | des_user_floor[8:0]};
	 10:des_floor = {5'b0,des_cu_floor[9:0] | des_user_floor[9:0]};
	 11:des_floor = {4'b0,des_cu_floor[10:0] | des_user_floor[10:0]};
	 12:des_floor = {3'b0,des_cu_floor[11:0] | des_user_floor[11:0]};
	 13:des_floor = {2'b0,des_cu_floor[12:0] | des_user_floor[12:0]};
	 14:des_floor = {1'b0,des_cu_floor[13:0] | des_user_floor[13:0]};
	 15:des_floor = {des_cu_floor[14:0] | des_user_floor[14:0]};
    endcase
  else  des_floor = des_cu_floor | des_user_floor;
end





always @ (posedge clk or negedge reset )
begin
if(!reset) DESLE = 0;
else
	if(state == S3 &&bye ==1&&or_des== 0)
	  DESLE = 1; 
 else DESLE = 0;//=1时清除DSE	; 

end

always @ (posedge clk or negedge reset)
begin
if( !reset) start_j=1;
else if (stay_s1 == 1)	start_j=0;
else
  if(start_j <10)	start_j=start_j+1;
  else 	 start_j=start_j;
end

always @ (posedge clk or negedge reset)
begin
if( !reset) start_i=1;
else if (stay_s0 == 1)	start_i=0;
else
  if(start_i <2)	start_i=start_i+1;
  else 	 start_i=start_i;
end



function  up_f;
input [3:0] cur_floor_f;
input [15:0] des_floor_f;
input up_in_f;
input wait_f;

begin
if(wait_f) up_f=up_in_f;
else begin
	if(up_in_f==1)
	case (cur_floor_f)
	0:up_f={|des_floor_f[15:0]};
	1:up_f={|des_floor_f[15:1]};
	2:up_f={|des_floor_f[15:2]};
	3:up_f={|des_floor_f[15:3]};
	4:up_f={|des_floor_f[15:4]};
	5:up_f={|des_floor_f[15:5]};
	6:up_f={|des_floor_f[15:6]};
	7:up_f={|des_floor_f[15:7]};
	8:up_f={|des_floor_f[15:8]};
	9:up_f={|des_floor_f[15:9]};
	10:up_f={|des_floor_f[15:10]};
	11:up_f={|des_floor_f[15:11]};
	12:up_f={|des_floor_f[15:12]};
	13:up_f={|des_floor_f[15:13]};
	14:up_f={|des_floor_f[15:14]};
	15:up_f=des_floor_f[15];
endcase
else   
	case (cur_floor_f)
	0:up_f= ~des_floor_f[0];
	1:up_f=~{|des_floor_f[1:0]};
	2:up_f=~{|des_floor_f[2:0]};
	3:up_f=~{|des_floor_f[3:0]};
	4:up_f=~{|des_floor_f[4:0]};
	5:up_f=~{|des_floor_f[5:0]};
	6:up_f=~{|des_floor_f[6:0]};
	7:up_f=~{|des_floor_f[7:0]};
	8:up_f=~{|des_floor_f[8:0]};
	9:up_f=~{|des_floor_f[9:0]};
	10:up_f=~{|des_floor_f[10:0]};
	11:up_f=~{|des_floor_f[11:0]};
	12:up_f=~{|des_floor_f[12:0]};
	13:up_f=~{|des_floor_f[13:0]};
	14:up_f=~{|des_floor_f[14:0]};
	15:up_f=~{|des_floor_f[15:0]};
	endcase
end
end
endfunction



function des_cu_is1;
input[3:0] cur_lift;
input [15:0] des_floor_ff;
begin
des_cu_is1 = 0;
case(cur_lift)
	'b0000: if (des_floor_ff[0] == 1) des_cu_is1 = 1;	
	'b0001: if (des_floor_ff[1] == 1) des_cu_is1 = 1;
	'b0010: if (des_floor_ff[2] == 1) des_cu_is1 = 1;
	'b0011: if (des_floor_ff[3] == 1) des_cu_is1 = 1;
	'b0100: if (des_floor_ff[4] == 1) des_cu_is1 = 1;
	'b0101: if (des_floor_ff[5] == 1) des_cu_is1 = 1;
	'b0110: if (des_floor_ff[6] == 1) des_cu_is1 = 1;
	'b0111: if (des_floor_ff[7] == 1) des_cu_is1 = 1;
	'b1000: if (des_floor_ff[8] == 1) des_cu_is1 = 1;
	'b1001: if (des_floor_ff[9] == 1) des_cu_is1 = 1;
	'b1010: if (des_floor_ff[10] == 1) des_cu_is1 = 1;
	'b1011: if (des_floor_ff[11] == 1) des_cu_is1 = 1;
	'b1100: if (des_floor_ff[12] == 1) des_cu_is1 = 1;
	'b1101: if (des_floor_ff[13] == 1) des_cu_is1 = 1;
	'b1110: if (des_floor_ff[14] == 1) des_cu_is1 = 1;
	'b1111: if (des_floor_ff[15] == 1) des_cu_is1 = 1;
endcase
end
endfunction




endmodule