cnt10.map.qmsg

来自「带复位和时钟使能的十进制计数器 verilo 描述」· QMSG 代码 · 共 18 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 21 11:19:39 2008 " "Info: Processing started: Fri Nov 21 11:19:39 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cnt10 -c cnt10 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt10 -c cnt10" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt10-bhh " "Info: Found design unit 1: cnt10-bhh" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cnt10 " "Info: Elaborating entity \"cnt10\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cnt10.vhd(63) " "Info: VHDL Case Statement information at cnt10.vhd(63): OTHERS choice is never selected" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led7s cnt10.vhd(34) " "Warning: VHDL Process Statement warning at cnt10.vhd(34): signal or variable \"led7s\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"led7s\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[0\]\$latch " "Warning: Latch led7s\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[1\]\$latch " "Warning: Latch led7s\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[2\]\$latch " "Warning: Latch led7s\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[3\]\$latch " "Warning: Latch led7s\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[4\]\$latch " "Warning: Latch led7s\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[5\]\$latch " "Warning: Latch led7s\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led7s\[6\]\$latch " "Warning: Latch led7s\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cqi\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal cqi\[0\]" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0}  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[0\] VCC " "Warning: Pin \"cout\[0\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[1\] VCC " "Warning: Pin \"cout\[1\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[2\] VCC " "Warning: Pin \"cout\[2\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[3\] VCC " "Warning: Pin \"cout\[3\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[4\] VCC " "Warning: Pin \"cout\[4\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[5\] VCC " "Warning: Pin \"cout\[5\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout\[6\] VCC " "Warning: Pin \"cout\[6\]\" stuck at VCC" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "57 " "Info: Implemented 57 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "23 " "Info: Implemented 23 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 21 11:19:41 2008 " "Info: Processing ended: Fri Nov 21 11:19:41 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}