cnt10.fit.qmsg

带复位和时钟使能的十进制计数器 verilo 描述

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 21 11:19:43 2008 " "Info: Processing started: Fri Nov 21 11:19:43 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off cnt10 -c cnt10 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off cnt10 -c cnt10" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "cnt10 EP1C20F324C8 " "Info: Selected device EP1C20F324C8 for design \"cnt10\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F324C8 " "Info: Device EP1C4F324C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F324C8 " "Info: Device EP1C12F324C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN J16 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN J16" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "Mux~302 Global clock " "Info: Automatically promoted signal \"Mux~302\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Mux~302" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { Mux~302 } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { Mux~302 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rest Global clock " "Info: Automatically promoted signal \"rest\" to use Global clock" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rest " "Info: Pin \"rest\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rest" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { rest } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { rest } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.934 ns register register " "Info: Estimated most critical path is register to register delay of 0.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cqi\[3\] 1 REG LAB_X6_Y13 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y13; Fanout = 13; REG Node = 'cqi\[3\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.625 ns) + CELL(0.309 ns) 0.934 ns cqi\[1\] 2 REG LAB_X6_Y13 13 " "Info: 2: + IC(0.625 ns) + CELL(0.309 ns) = 0.934 ns; Loc. = LAB_X6_Y13; Fanout = 13; REG Node = 'cqi\[1\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "0.934 ns" { cqi[3] cqi[1] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 33.08 % " "Info: Total cell delay = 0.309 ns ( 33.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.625 ns 66.92 % " "Info: Total interconnect delay = 0.625 ns ( 66.92 % )" {  } {  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "0.934 ns" { cqi[3] cqi[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "7 " "Warning: The following 7 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[0\] VCC " "Info: Pin cout\[0\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[0\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[0] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[1\] VCC " "Info: Pin cout\[1\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[1\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[1] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[2\] VCC " "Info: Pin cout\[2\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[2\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[2] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[3\] VCC " "Info: Pin cout\[3\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[3\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[3] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[4\] VCC " "Info: Pin cout\[4\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[4\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[4] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[5\] VCC " "Info: Pin cout\[5\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[5\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[5] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cout\[6\] VCC " "Info: Pin cout\[6\] has VCC driving its datain port" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout\[6\]" } } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cout[6] } "NODE_NAME" } "" } } { "E:/实验8/cnt10.fld" "" { Floorplan "E:/实验8/cnt10.fld" "" "" { cout[6] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 21 11:19:52 2008 " "Info: Processing ended: Fri Nov 21 11:19:52 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}