cnt10.tan.rpt

带复位和时钟使能的十进制计数器 verilo 描述

; N/A   ; None         ; 13.081 ns  ; cqi[1] ; led7s[2] ; clk        ;
; N/A   ; None         ; 13.076 ns  ; cqi[3] ; cout[7]  ; clk        ;
; N/A   ; None         ; 12.989 ns  ; cqi[1] ; led7s[1] ; clk        ;
; N/A   ; None         ; 12.934 ns  ; cqi[3] ; led7s[2] ; clk        ;
; N/A   ; None         ; 12.842 ns  ; cqi[3] ; led7s[1] ; clk        ;
+-------+--------------+------------+--------+----------+------------+


+--------------------------------------------------------------------+
; tpd                                                                ;
+-------+-------------------+-----------------+------+---------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To            ;
+-------+-------------------+-----------------+------+---------------+
; N/A   ; None              ; 19.090 ns       ; b[1] ; led_selout[3] ;
; N/A   ; None              ; 19.088 ns       ; b[1] ; led_selout[7] ;
; N/A   ; None              ; 19.087 ns       ; b[1] ; led_selout[4] ;
; N/A   ; None              ; 19.085 ns       ; b[1] ; led_selout[6] ;
; N/A   ; None              ; 19.082 ns       ; b[1] ; led_selout[5] ;
; N/A   ; None              ; 19.081 ns       ; b[1] ; led_selout[2] ;
; N/A   ; None              ; 19.080 ns       ; b[1] ; led_selout[0] ;
; N/A   ; None              ; 18.637 ns       ; b[1] ; led_selout[1] ;
; N/A   ; None              ; 17.148 ns       ; b[0] ; led_selout[0] ;
; N/A   ; None              ; 17.145 ns       ; b[0] ; led_selout[2] ;
; N/A   ; None              ; 17.143 ns       ; b[0] ; led_selout[5] ;
; N/A   ; None              ; 17.142 ns       ; b[0] ; led_selout[6] ;
; N/A   ; None              ; 17.139 ns       ; b[0] ; led_selout[4] ;
; N/A   ; None              ; 17.136 ns       ; b[0] ; led_selout[7] ;
; N/A   ; None              ; 17.135 ns       ; b[0] ; led_selout[3] ;
; N/A   ; None              ; 16.903 ns       ; b[2] ; led_selout[3] ;
; N/A   ; None              ; 16.900 ns       ; b[2] ; led_selout[7] ;
; N/A   ; None              ; 16.900 ns       ; b[2] ; led_selout[4] ;
; N/A   ; None              ; 16.898 ns       ; b[2] ; led_selout[6] ;
; N/A   ; None              ; 16.894 ns       ; b[2] ; led_selout[5] ;
; N/A   ; None              ; 16.892 ns       ; b[2] ; led_selout[2] ;
; N/A   ; None              ; 16.892 ns       ; b[2] ; led_selout[0] ;
; N/A   ; None              ; 16.709 ns       ; b[0] ; led_selout[1] ;
; N/A   ; None              ; 16.450 ns       ; b[2] ; led_selout[1] ;
+-------+-------------------+-----------------+------+---------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -5.793 ns ; en   ; cqi[1] ; clk      ;
; N/A           ; None        ; -5.793 ns ; en   ; cqi[3] ; clk      ;
; N/A           ; None        ; -5.793 ns ; en   ; cqi[0] ; clk      ;
; N/A           ; None        ; -5.793 ns ; en   ; cqi[2] ; clk      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Nov 21 11:20:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt10 -c cnt10 --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "led7s[0]$latch" is a latch
    Warning: Node "led7s[1]$latch" is a latch
    Warning: Node "led7s[2]$latch" is a latch
    Warning: Node "led7s[3]$latch" is a latch
    Warning: Node "led7s[4]$latch" is a latch
    Warning: Node "led7s[5]$latch" is a latch
    Warning: Node "led7s[6]$latch" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[6]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[5]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[4]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[3]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[2]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[1]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "led7s[0]$latch"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "cqi[0]" and destination register "cqi[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.462 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi[0]'
            Info: 2: + IC(0.724 ns) + CELL(0.738 ns) = 1.462 ns; Loc. = LC_X6_Y13_N5; Fanout = 12; REG Node = 'cqi[2]'
            Info: Total cell delay = 0.738 ns ( 50.48 % )
            Info: Total interconnect delay = 0.724 ns ( 49.52 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.109 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N5; Fanout = 12; REG Node = 'cqi[2]'
                Info: Total cell delay = 2.180 ns ( 70.12 % )
                Info: Total interconnect delay = 0.929 ns ( 29.88 % )
            Info: - Longest clock path from clock "clk" to source register is 3.109 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi[0]'
                Info: Total cell delay = 2.180 ns ( 70.12 % )
                Info: Total interconnect delay = 0.929 ns ( 29.88 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "cqi[1]" (data pin = "en", clock pin = "clk") is 5.845 ns
    Info: + Longest pin to register delay is 8.917 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_P3; Fanout = 4; PIN Node = 'en'
        Info: 2: + IC(6.581 ns) + CELL(0.867 ns) = 8.917 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi[1]'
        Info: Total cell delay = 2.336 ns ( 26.20 % )
        Info: Total interconnect delay = 6.581 ns ( 73.80 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.109 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi[1]'
        Info: Total cell delay = 2.180 ns ( 70.12 % )
        Info: Total interconnect delay = 0.929 ns ( 29.88 % )
Info: tco from clock "clk" to destination pin "led7s[4]" through register "cqi[0]" is 14.581 ns
    Info: + Longest clock path from clock "clk" to source register is 3.109 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi[0]'
        Info: Total cell delay = 2.180 ns ( 70.12 % )
        Info: Total interconnect delay = 0.929 ns ( 29.88 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 11.248 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi[0]'
        Info: 2: + IC(0.724 ns) + CELL(0.590 ns) = 1.314 ns; Loc. = LC_X6_Y13_N6; Fanout = 14; COMB Node = 'Mux~302'
        Info: 3: + IC(0.000 ns) + CELL(5.046 ns) = 6.360 ns; Loc. = LC_X5_Y13_N4; Fanout = 2; COMB LOOP Node = 'led7s[4]$latch'
            Info: Loc. = LC_X5_Y13_N4; Node "led7s[4]$latch"
        Info: 4: + IC(2.764 ns) + CELL(2.124 ns) = 11.248 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'led7s[4]'
        Info: Total cell delay = 7.760 ns ( 68.99 % )
        Info: Total interconnect delay = 3.488 ns ( 31.01 % )
Info: Longest tpd from source pin "b[1]" to destination pin "led_selout[3]" is 19.090 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_N14; Fanout = 8; PIN Node = 'b[1]'
    Info: 2: + IC(13.375 ns) + CELL(0.590 ns) = 15.434 ns; Loc. = LC_X1_Y26_N2; Fanout = 1; COMB Node = 'Mux~296'
    Info: 3: + IC(1.532 ns) + CELL(2.124 ns) = 19.090 ns; Loc. = PIN_F2; Fanout = 0; PIN Node = 'led_selout[3]'
    Info: Total cell delay = 4.183 ns ( 21.91 % )
    Info: Total interconnect delay = 14.907 ns ( 78.09 % )
Info: th for register "cqi[1]" (data pin = "en", clock pin = "clk") is -5.793 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.109 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi[1]'
        Info: Total cell delay = 2.180 ns ( 70.12 % )
        Info: Total interconnect delay = 0.929 ns ( 29.88 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.917 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_P3; Fanout = 4; PIN Node = 'en'
        Info: 2: + IC(6.581 ns) + CELL(0.867 ns) = 8.917 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi[1]'
        Info: Total cell delay = 2.336 ns ( 26.20 % )
        Info: Total interconnect delay = 6.581 ns ( 73.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 9 warnings
    Info: Processing ended: Fri Nov 21 11:20:00 2008
    Info: Elapsed time: 00:00:01