📄 cnt10.tan.rpt
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Timing Analyzer report for cnt10
Fri Nov 21 11:20:00 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------+---------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.845 ns ; en ; cqi[2] ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 14.581 ns ; cqi[0] ; led7s[4] ; clk ; ; 0 ;
; Worst-case tpd ; N/A ; None ; 19.090 ns ; b[1] ; led_selout[3] ; ; ; 0 ;
; Worst-case th ; N/A ; None ; -5.793 ns ; en ; cqi[2] ; ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[0] ; cqi[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C20F324C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[0] ; cqi[2] ; clk ; clk ; None ; None ; 1.462 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[0] ; cqi[1] ; clk ; clk ; None ; None ; 1.461 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[0] ; cqi[3] ; clk ; clk ; None ; None ; 1.448 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[0] ; cqi[0] ; clk ; clk ; None ; None ; 1.444 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[2] ; cqi[0] ; clk ; clk ; None ; None ; 1.290 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[2] ; cqi[3] ; clk ; clk ; None ; None ; 1.289 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[2] ; cqi[2] ; clk ; clk ; None ; None ; 1.265 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[1] ; cqi[0] ; clk ; clk ; None ; None ; 1.210 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[1] ; cqi[3] ; clk ; clk ; None ; None ; 1.209 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[1] ; cqi[2] ; clk ; clk ; None ; None ; 1.196 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[1] ; cqi[1] ; clk ; clk ; None ; None ; 1.194 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[3] ; cqi[2] ; clk ; clk ; None ; None ; 1.058 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[3] ; cqi[1] ; clk ; clk ; None ; None ; 1.055 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[3] ; cqi[0] ; clk ; clk ; None ; None ; 1.046 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cqi[3] ; cqi[3] ; clk ; clk ; None ; None ; 1.044 ns ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 5.845 ns ; en ; cqi[1] ; clk ;
; N/A ; None ; 5.845 ns ; en ; cqi[3] ; clk ;
; N/A ; None ; 5.845 ns ; en ; cqi[0] ; clk ;
; N/A ; None ; 5.845 ns ; en ; cqi[2] ; clk ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----------+------------+
; N/A ; None ; 14.581 ns ; cqi[0] ; led7s[4] ; clk ;
; N/A ; None ; 14.373 ns ; cqi[2] ; led7s[4] ; clk ;
; N/A ; None ; 14.276 ns ; cqi[1] ; led7s[4] ; clk ;
; N/A ; None ; 14.129 ns ; cqi[3] ; led7s[4] ; clk ;
; N/A ; None ; 13.725 ns ; cqi[0] ; led7s[3] ; clk ;
; N/A ; None ; 13.671 ns ; cqi[0] ; led7s[5] ; clk ;
; N/A ; None ; 13.620 ns ; cqi[0] ; led7s[0] ; clk ;
; N/A ; None ; 13.565 ns ; cqi[0] ; led7s[6] ; clk ;
; N/A ; None ; 13.527 ns ; cqi[0] ; cout[7] ; clk ;
; N/A ; None ; 13.517 ns ; cqi[2] ; led7s[3] ; clk ;
; N/A ; None ; 13.463 ns ; cqi[2] ; led7s[5] ; clk ;
; N/A ; None ; 13.420 ns ; cqi[1] ; led7s[3] ; clk ;
; N/A ; None ; 13.412 ns ; cqi[2] ; led7s[0] ; clk ;
; N/A ; None ; 13.386 ns ; cqi[0] ; led7s[2] ; clk ;
; N/A ; None ; 13.366 ns ; cqi[1] ; led7s[5] ; clk ;
; N/A ; None ; 13.357 ns ; cqi[2] ; led7s[6] ; clk ;
; N/A ; None ; 13.339 ns ; cqi[2] ; cout[7] ; clk ;
; N/A ; None ; 13.315 ns ; cqi[1] ; led7s[0] ; clk ;
; N/A ; None ; 13.294 ns ; cqi[0] ; led7s[1] ; clk ;
; N/A ; None ; 13.273 ns ; cqi[3] ; led7s[3] ; clk ;
; N/A ; None ; 13.260 ns ; cqi[1] ; led7s[6] ; clk ;
; N/A ; None ; 13.237 ns ; cqi[1] ; cout[7] ; clk ;
; N/A ; None ; 13.219 ns ; cqi[3] ; led7s[5] ; clk ;
; N/A ; None ; 13.178 ns ; cqi[2] ; led7s[2] ; clk ;
; N/A ; None ; 13.168 ns ; cqi[3] ; led7s[0] ; clk ;
; N/A ; None ; 13.113 ns ; cqi[3] ; led7s[6] ; clk ;
; N/A ; None ; 13.086 ns ; cqi[2] ; led7s[1] ; clk ;
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