sdr_sdram.srr

SDRAM控制器的VHDL代码在FGPA中的综合与实现

$ Start of Compile
#Wed Oct 10 23:24:40 2001

Synplicity Verilog Compiler, version 6.2.0, Build 097R, built Apr 16 2001
Copyright (C) 1994-2000, Synplicity Inc.  All Rights Reserved

@E|Can't open file d:\projects\altera\lpcores\sdr\release\v1_2\source\control_interface.v
@END
Process took 0.0600001 seconds realtime, 0.06 seconds cputime