sw_debounce.tan.qmsg

verilog键盘防抖程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[18\] register low_sw\[0\] 220.8 MHz 4.529 ns Internal " "Info: Clock \"clk\" has Internal fmax of 220.8 MHz between source register \"cnt\[18\]\" and destination register \"low_sw\[0\]\" (period= 4.529 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.270 ns + Longest register register " "Info: + Longest register to register delay is 4.270 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[18\] 1 REG LCFF_X32_Y9_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y9_N17; Fanout = 3; REG Node = 'cnt\[18\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[18] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.614 ns) 2.134 ns Equal0~196 2 COMB LCCOMB_X31_Y10_N14 1 " "Info: 2: + IC(1.520 ns) + CELL(0.614 ns) = 2.134 ns; Loc. = LCCOMB_X31_Y10_N14; Fanout = 1; COMB Node = 'Equal0~196'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.134 ns" { cnt[18] Equal0~196 } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.589 ns) 3.089 ns Equal0~197 3 COMB LCCOMB_X31_Y10_N26 4 " "Info: 3: + IC(0.366 ns) + CELL(0.589 ns) = 3.089 ns; Loc. = LCCOMB_X31_Y10_N26; Fanout = 4; COMB Node = 'Equal0~197'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.955 ns" { Equal0~196 Equal0~197 } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.855 ns) 4.270 ns low_sw\[0\] 4 REG LCFF_X31_Y10_N1 3 " "Info: 4: + IC(0.326 ns) + CELL(0.855 ns) = 4.270 ns; Loc. = LCFF_X31_Y10_N1; Fanout = 3; REG Node = 'low_sw\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.181 ns" { Equal0~197 low_sw[0] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.058 ns ( 48.20 % ) " "Info: Total cell delay = 2.058 ns ( 48.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.212 ns ( 51.80 % ) " "Info: Total interconnect delay = 2.212 ns ( 51.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.270 ns" { cnt[18] Equal0~196 Equal0~197 low_sw[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.270 ns" { cnt[18] Equal0~196 Equal0~197 low_sw[0] } { 0.000ns 1.520ns 0.366ns 0.326ns } { 0.000ns 0.614ns 0.589ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.005 ns - Smallest " "Info: - Smallest clock skew is 0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.095 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.666 ns) 3.095 ns low_sw\[0\] 3 REG LCFF_X31_Y10_N1 3 " "Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N1; Fanout = 3; REG Node = 'low_sw\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { clk~clkctrl low_sw[0] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.06 % ) " "Info: Total cell delay = 1.766 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.329 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.329 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[0] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.090 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.666 ns) 3.090 ns cnt\[18\] 3 REG LCFF_X32_Y9_N17 3 " "Info: 3: + IC(1.067 ns) + CELL(0.666 ns) = 3.090 ns; Loc. = LCFF_X32_Y9_N17; Fanout = 3; REG Node = 'cnt\[18\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.733 ns" { clk~clkctrl cnt[18] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.15 % ) " "Info: Total cell delay = 1.766 ns ( 57.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.324 ns ( 42.85 % ) " "Info: Total interconnect delay = 1.324 ns ( 42.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { clk clk~clkctrl cnt[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { clk clk~combout clk~clkctrl cnt[18] } { 0.000ns 0.000ns 0.257ns 1.067ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[0] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { clk clk~clkctrl cnt[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { clk clk~combout clk~clkctrl cnt[18] } { 0.000ns 0.000ns 0.257ns 1.067ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 37 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.270 ns" { cnt[18] Equal0~196 Equal0~197 low_sw[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.270 ns" { cnt[18] Equal0~196 Equal0~197 low_sw[0] } { 0.000ns 1.520ns 0.366ns 0.326ns } { 0.000ns 0.614ns 0.589ns 0.855ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[0] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { clk clk~clkctrl cnt[18] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { clk clk~combout clk~clkctrl cnt[18] } { 0.000ns 0.000ns 0.257ns 1.067ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "low_sw\[2\] sw3_n clk 6.653 ns register " "Info: tsu for register \"low_sw\[2\]\" (data pin = \"sw3_n\", clock pin = \"clk\") is 6.653 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.788 ns + Longest pin register " "Info: + Longest pin to register delay is 9.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns sw3_n 1 PIN PIN_R15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_R15; Fanout = 1; PIN Node = 'sw3_n'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw3_n } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.901 ns) + CELL(0.202 ns) 8.027 ns low_sw\[2\]~134 2 COMB LCCOMB_X31_Y9_N24 2 " "Info: 2: + IC(6.901 ns) + CELL(0.202 ns) = 8.027 ns; Loc. = LCCOMB_X31_Y9_N24; Fanout = 2; COMB Node = 'low_sw\[2\]~134'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.103 ns" { sw3_n low_sw[2]~134 } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.447 ns) + CELL(0.206 ns) 9.680 ns low_sw\[2\]~feeder 3 COMB LCCOMB_X31_Y10_N8 1 " "Info: 3: + IC(1.447 ns) + CELL(0.206 ns) = 9.680 ns; Loc. = LCCOMB_X31_Y10_N8; Fanout = 1; COMB Node = 'low_sw\[2\]~feeder'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.653 ns" { low_sw[2]~134 low_sw[2]~feeder } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.788 ns low_sw\[2\] 4 REG LCFF_X31_Y10_N9 3 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 9.788 ns; Loc. = LCFF_X31_Y10_N9; Fanout = 3; REG Node = 'low_sw\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { low_sw[2]~feeder low_sw[2] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.440 ns ( 14.71 % ) " "Info: Total cell delay = 1.440 ns ( 14.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.348 ns ( 85.29 % ) " "Info: Total interconnect delay = 8.348 ns ( 85.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.788 ns" { sw3_n low_sw[2]~134 low_sw[2]~feeder low_sw[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.788 ns" { sw3_n sw3_n~combout low_sw[2]~134 low_sw[2]~feeder low_sw[2] } { 0.000ns 0.000ns 6.901ns 1.447ns 0.000ns } { 0.000ns 0.924ns 0.202ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.095 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.666 ns) 3.095 ns low_sw\[2\] 3 REG LCFF_X31_Y10_N9 3 " "Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N9; Fanout = 3; REG Node = 'low_sw\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { clk~clkctrl low_sw[2] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.06 % ) " "Info: Total cell delay = 1.766 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.329 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.329 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[2] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.788 ns" { sw3_n low_sw[2]~134 low_sw[2]~feeder low_sw[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.788 ns" { sw3_n sw3_n~combout low_sw[2]~134 low_sw[2]~feeder low_sw[2] } { 0.000ns 0.000ns 6.901ns 1.447ns 0.000ns } { 0.000ns 0.924ns 0.202ns 0.206ns 0.108ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[2] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk outh_d\[3\] low_sw\[3\] 10.388 ns register " "Info: tco from clock \"clk\" to destination pin \"outh_d\[3\]\" through register \"low_sw\[3\]\" is 10.388 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.095 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.666 ns) 3.095 ns low_sw\[3\] 3 REG LCFF_X31_Y10_N29 3 " "Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { clk~clkctrl low_sw[3] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.06 % ) " "Info: Total cell delay = 1.766 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.329 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.329 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[3] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.989 ns + Longest register pin " "Info: + Longest register to pin delay is 6.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns low_sw\[3\] 1 REG LCFF_X31_Y10_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { low_sw[3] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.783 ns) + CELL(3.206 ns) 6.989 ns outh_d\[3\] 2 PIN PIN_D15 0 " "Info: 2: + IC(3.783 ns) + CELL(3.206 ns) = 6.989 ns; Loc. = PIN_D15; Fanout = 0; PIN Node = 'outh_d\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.989 ns" { low_sw[3] outh_d[3] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.206 ns ( 45.87 % ) " "Info: Total cell delay = 3.206 ns ( 45.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.783 ns ( 54.13 % ) " "Info: Total interconnect delay = 3.783 ns ( 54.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.989 ns" { low_sw[3] outh_d[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.989 ns" { low_sw[3] outh_d[3] } { 0.000ns 3.783ns } { 0.000ns 3.206ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[3] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.989 ns" { low_sw[3] outh_d[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.989 ns" { low_sw[3] outh_d[3] } { 0.000ns 3.783ns } { 0.000ns 3.206ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "low_sw\[3\] sw4_n clk 0.212 ns register " "Info: th for register \"low_sw\[3\]\" (data pin = \"sw4_n\", clock pin = \"clk\") is 0.212 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.095 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.666 ns) 3.095 ns low_sw\[3\] 3 REG LCFF_X31_Y10_N29 3 " "Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { clk~clkctrl low_sw[3] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.06 % ) " "Info: Total cell delay = 1.766 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.329 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.329 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[3] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.189 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns sw4_n 1 PIN PIN_L21 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L21; Fanout = 1; PIN Node = 'sw4_n'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw4_n } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.611 ns) + CELL(0.370 ns) 3.081 ns low_sw\[3\]~135 2 COMB LCCOMB_X31_Y10_N28 2 " "Info: 2: + IC(1.611 ns) + CELL(0.370 ns) = 3.081 ns; Loc. = LCCOMB_X31_Y10_N28; Fanout = 2; COMB Node = 'low_sw\[3\]~135'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.981 ns" { sw4_n low_sw[3]~135 } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.189 ns low_sw\[3\] 3 REG LCFF_X31_Y10_N29 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.189 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { low_sw[3]~135 low_sw[3] } "NODE_NAME" } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.578 ns ( 49.48 % ) " "Info: Total cell delay = 1.578 ns ( 49.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.611 ns ( 50.52 % ) " "Info: Total interconnect delay = 1.611 ns ( 50.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sw4_n low_sw[3]~135 low_sw[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sw4_n sw4_n~combout low_sw[3]~135 low_sw[3] } { 0.000ns 0.000ns 1.611ns 0.000ns } { 0.000ns 1.100ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.095 ns" { clk clk~clkctrl low_sw[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.095 ns" { clk clk~combout clk~clkctrl low_sw[3] } { 0.000ns 0.000ns 0.257ns 1.072ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sw4_n low_sw[3]~135 low_sw[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sw4_n sw4_n~combout low_sw[3]~135 low_sw[3] } { 0.000ns 0.000ns 1.611ns 0.000ns } { 0.000ns 1.100ns 0.370ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}