sw_debounce.map.rpt

verilog键盘防抖程序

; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                      ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------+
; sw_debounce.v                    ; yes             ; User Verilog HDL File  ; E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 40    ;
;                                             ;       ;
; Total combinational functions               ; 38    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 8     ;
;     -- 3 input functions                    ; 4     ;
;     -- <=2 input functions                  ; 26    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 19    ;
;     -- arithmetic mode                      ; 19    ;
;                                             ;       ;
; Total registers                             ; 40    ;
;     -- Dedicated logic registers            ; 40    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 14    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 40    ;
; Total fan-out                               ; 243   ;
; Average fan-out                             ; 2.64  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |sw_debounce               ; 38 (38)           ; 40 (40)      ; 0           ; 0            ; 0       ; 0         ; 14   ; 0            ; |sw_debounce        ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 40    ;
; Number of registers using Synchronous Clear  ; 20    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 40    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; low_sw[0]                               ; 3       ;
; low_sw[1]                               ; 3       ;
; low_sw[2]                               ; 3       ;
; low_sw[3]                               ; 3       ;
; low_sw_r[0]                             ; 1       ;
; low_sw_r[1]                             ; 1       ;
; low_sw_r[2]                             ; 1       ;
; low_sw_r[3]                             ; 1       ;
; key_rst[0]                              ; 2       ;
; key_rst_r[0]                            ; 1       ;
; key_rst[1]                              ; 2       ;
; key_rst[3]                              ; 2       ;
; key_rst_r[1]                            ; 1       ;
; key_rst_r[3]                            ; 1       ;
; key_rst[2]                              ; 2       ;
; key_rst_r[2]                            ; 1       ;
; Total number of inverted registers = 16 ;         ;
+-----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Apr 26 17:37:50 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sw_debounce -c sw_debounce
Info: Found 1 design units, including 1 entities, in source file sw_debounce.v
    Info: Found entity 1: sw_debounce
Info: Elaborating entity "sw_debounce" for the top level hierarchy
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 68 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 8 output pins
    Info: Implemented 54 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 126 megabytes of memory during processing
    Info: Processing ended: Sun Apr 26 17:37:51 2009
    Info: Elapsed time: 00:00:01