sw_debounce.fit.smsg

verilog键盘防抖程序

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Apr 26 17:37:53 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sw_debounce -c sw_debounce
Info: Selected device EP2C20F484C8 for design "sw_debounce"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C15AF484C8 is compatible
    Info: Device EP2C15AF484I8 is compatible
    Info: Device EP2C20F484I8 is compatible
    Info: Device EP2C20AF484I8 is compatible
    Info: Device EP2C35F484C8 is compatible
    Info: Device EP2C35F484I8 is compatible
    Info: Device EP2C50F484C8 is compatible
    Info: Device EP2C50F484I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location C4
    Info: Pin ~nCSO~ is reserved at location C3
    Info: Pin ~LVDS91p/nCEO~ is reserved at location W20
Warning: No exact pin location assignment(s) for 5 pins of 14 total pins
    Info: Pin sw_d1 not assigned to an exact location on the device
    Info: Pin sw_d2 not assigned to an exact location on the device
    Info: Pin sw_d3 not assigned to an exact location on the device
    Info: Pin sw_d4 not assigned to an exact location on the device
    Info: Pin rst_n not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN L1 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node rst_n (placed in PIN L2 (CLK1, LVDSCLK0n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 4 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  41 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  29 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  36 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  35 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  37 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.145 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y11; Fanout = 2; REG Node = 'key_rst[1]'
    Info: 2: + IC(0.945 ns) + CELL(0.650 ns) = 1.595 ns; Loc. = LAB_X31_Y10; Fanout = 1; COMB Node = 'WideOr0~9'
    Info: 3: + IC(0.187 ns) + CELL(0.624 ns) = 2.406 ns; Loc. = LAB_X31_Y10; Fanout = 20; COMB Node = 'WideOr0'
    Info: 4: + IC(1.079 ns) + CELL(0.660 ns) = 4.145 ns; Loc. = LAB_X32_Y9; Fanout = 3; REG Node = 'cnt[10]'
    Info: Total cell delay = 1.934 ns ( 46.66 % )
    Info: Total interconnect delay = 2.211 ns ( 53.34 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X25_Y0 to location X37_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 8 output pins without output pin load capacitance assignment
    Info: Pin "sw_d1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "sw_d2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "sw_d3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "sw_d4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "outh_d[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "outh_d[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "outh_d[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "outh_d[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 193 megabytes of memory during processing
    Info: Processing ended: Sun Apr 26 17:38:00 2009
    Info: Elapsed time: 00:00:07