sw_debounce.tan.rpt

verilog键盘防抖程序

+---------------+-------------+-----------+-------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Apr 26 17:38:13 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sw_debounce -c sw_debounce --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 220.8 MHz between source register "cnt[18]" and destination register "low_sw[0]" (period= 4.529 ns)
    Info: + Longest register to register delay is 4.270 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y9_N17; Fanout = 3; REG Node = 'cnt[18]'
        Info: 2: + IC(1.520 ns) + CELL(0.614 ns) = 2.134 ns; Loc. = LCCOMB_X31_Y10_N14; Fanout = 1; COMB Node = 'Equal0~196'
        Info: 3: + IC(0.366 ns) + CELL(0.589 ns) = 3.089 ns; Loc. = LCCOMB_X31_Y10_N26; Fanout = 4; COMB Node = 'Equal0~197'
        Info: 4: + IC(0.326 ns) + CELL(0.855 ns) = 4.270 ns; Loc. = LCFF_X31_Y10_N1; Fanout = 3; REG Node = 'low_sw[0]'
        Info: Total cell delay = 2.058 ns ( 48.20 % )
        Info: Total interconnect delay = 2.212 ns ( 51.80 % )
    Info: - Smallest clock skew is 0.005 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.095 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N1; Fanout = 3; REG Node = 'low_sw[0]'
            Info: Total cell delay = 1.766 ns ( 57.06 % )
            Info: Total interconnect delay = 1.329 ns ( 42.94 % )
        Info: - Longest clock path from clock "clk" to source register is 3.090 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.067 ns) + CELL(0.666 ns) = 3.090 ns; Loc. = LCFF_X32_Y9_N17; Fanout = 3; REG Node = 'cnt[18]'
            Info: Total cell delay = 1.766 ns ( 57.15 % )
            Info: Total interconnect delay = 1.324 ns ( 42.85 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "low_sw[2]" (data pin = "sw3_n", clock pin = "clk") is 6.653 ns
    Info: + Longest pin to register delay is 9.788 ns
        Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_R15; Fanout = 1; PIN Node = 'sw3_n'
        Info: 2: + IC(6.901 ns) + CELL(0.202 ns) = 8.027 ns; Loc. = LCCOMB_X31_Y9_N24; Fanout = 2; COMB Node = 'low_sw[2]~134'
        Info: 3: + IC(1.447 ns) + CELL(0.206 ns) = 9.680 ns; Loc. = LCCOMB_X31_Y10_N8; Fanout = 1; COMB Node = 'low_sw[2]~feeder'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 9.788 ns; Loc. = LCFF_X31_Y10_N9; Fanout = 3; REG Node = 'low_sw[2]'
        Info: Total cell delay = 1.440 ns ( 14.71 % )
        Info: Total interconnect delay = 8.348 ns ( 85.29 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.095 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N9; Fanout = 3; REG Node = 'low_sw[2]'
        Info: Total cell delay = 1.766 ns ( 57.06 % )
        Info: Total interconnect delay = 1.329 ns ( 42.94 % )
Info: tco from clock "clk" to destination pin "outh_d[3]" through register "low_sw[3]" is 10.388 ns
    Info: + Longest clock path from clock "clk" to source register is 3.095 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw[3]'
        Info: Total cell delay = 1.766 ns ( 57.06 % )
        Info: Total interconnect delay = 1.329 ns ( 42.94 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.989 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw[3]'
        Info: 2: + IC(3.783 ns) + CELL(3.206 ns) = 6.989 ns; Loc. = PIN_D15; Fanout = 0; PIN Node = 'outh_d[3]'
        Info: Total cell delay = 3.206 ns ( 45.87 % )
        Info: Total interconnect delay = 3.783 ns ( 54.13 % )
Info: th for register "low_sw[3]" (data pin = "sw4_n", clock pin = "clk") is 0.212 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.095 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.072 ns) + CELL(0.666 ns) = 3.095 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw[3]'
        Info: Total cell delay = 1.766 ns ( 57.06 % )
        Info: Total interconnect delay = 1.329 ns ( 42.94 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.189 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L21; Fanout = 1; PIN Node = 'sw4_n'
        Info: 2: + IC(1.611 ns) + CELL(0.370 ns) = 3.081 ns; Loc. = LCCOMB_X31_Y10_N28; Fanout = 2; COMB Node = 'low_sw[3]~135'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.189 ns; Loc. = LCFF_X31_Y10_N29; Fanout = 3; REG Node = 'low_sw[3]'
        Info: Total cell delay = 1.578 ns ( 49.48 % )
        Info: Total interconnect delay = 1.611 ns ( 50.52 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Sun Apr 26 17:38:14 2009
    Info: Elapsed time: 00:00:01