h_adder.vhd

来自「计数器、频率计、优先编码器、数码管扫描电路、数据选择器」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
	PORT(
		a,b		: IN	STD_LOGIC;
		co,so	: OUT	STD_LOGIC);
END h_adder;
ARCHITECTURE art2 OF h_adder IS
	--SIGNAL __signal_name : STD_LOGIC;
	--SIGNAL __signal_name : STD_LOGIC;
BEGIN
	so<=a xor b;
	co<=a and b;
END art2;