f_adder.vhd

来自「计数器、频率计、优先编码器、数码管扫描电路、数据选择器」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_adder IS
	PORT( ain,bin,cin	: IN	STD_LOGIC;
		  cout,sum		: OUT	STD_LOGIC);
END f_adder;
ARCHITECTURE a OF f_adder IS
 component h_adder 
	port ( a,b : In std_logic;
			co,so: out std_logic);
 end component;
 component orm2 
	port ( a,b : In std_logic;
			c  : out std_logic);
 end component;
 
signal d,e,f :std_logic;
	begin 
	u1 : h_adder port map (a=>ain , b=>bin , co=>d , so=>e);
	u2 : h_adder port map (a=>e , b=>cin , co=>f , so=>sum);
	u3 : orm2 	 port map (a=>d , b=>f , c=>cout);
END a;