dff1.vhd

来自「计数器、频率计、优先编码器、数码管扫描电路、数据选择器」· VHDL 代码 · 共 21 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dff1 IS
	
	PORT(clk,clrn,prn,ena,d: IN	STD_LOGIC;
		               q2  : buffer	STD_LOGIC);
END dff1;
ARCHITECTURE d OF dff1 IS	
BEGIN
process(clk,clrn,prn)
  begin
    if clrn='0' and prn='1'  then  q2<='0';
    elsif clrn='1' and prn='0'  then  q2<='1';
    elsif clrn='0' and prn='0'  then  q2<=q2;
	elsif clk'event and clk='1'  then  
       if ena='1'  and d='0' then q2<='0';end if;
	   if ena='1'  and d='1' then q2<='1';end if;  
	   if ena='0'   then null;	end if;
   end if;   
end process;
end d;