jkff.vhd

来自「计数器、频率计、优先编码器、数码管扫描电路、数据选择器」· VHDL 代码 · 共 23 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY jk IS
	
	PORT(clk,clr,pset,j,k: IN	STD_LOGIC;
		               q,qb   : buffer	STD_LOGIC);
END jk;
ARCHITECTURE jk1 OF jk IS	
BEGIN
process(pset,clk,clr)
  begin
    if clr='1' and pset='0'  then  q<='1';qb<='0';
    	elsif clr='0' and pset='1'  then  q<='0';qb<='1';
    	elsif clk'event and clk='1' then
       			if j='0' and k='1' then q<='0';qb<='1';
      				elsif j='1' and k='1' then q<=not q; qb<=not qb;
       				elsif j='0' and k='0' then q<= q; qb<=not q;
       				elsif j='1' and k='0' then q<='1'; qb<='0';
       			end if;
       	end if;
end process;	
END jk1;