fpq.vhd

来自「计数器、频率计、优先编码器、数码管扫描电路、数据选择器」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fpq IS
		PORT(   clk		: IN  STD_LOGIC;
				y		: buffer STD_LOGIC);
END fpq;

ARCHITECTURE a OF fpq IS
SIGNAL q:STD_LOGIC;
BEGIN
P:process(clk)

BEGIN
	IF(clk'EVENT AND clk='1')THEN
		y<=not y;
	END if;
END process;
END a;