rciii.map.qmsg

niosII基础上实现的嵌入式网络驱动

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "firmware_ROM rcIII:inst\|firmware_ROM:the_firmware_ROM " "Info: Elaborating entity \"firmware_ROM\" for hierarchy \"rcIII:inst\|firmware_ROM:the_firmware_ROM\"" {  } { { "rcIII.v" "the_firmware_ROM" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3359 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rcIII:inst\|firmware_ROM:the_firmware_ROM\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rcIII:inst\|firmware_ROM:the_firmware_ROM\|altsyncram:the_altsyncram\"" {  } { { "firmware_ROM.v" "the_altsyncram" { Text "C:/altera/kits/nios2/components/rcIII/system/firmware_ROM.v" 85 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gq01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gq01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gq01 " "Info: Found entity 1: altsyncram_gq01" {  } { { "db/altsyncram_gq01.tdf" "" { Text "C:/altera/kits/nios2/components/rcIII/system/db/altsyncram_gq01.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gq01 rcIII:inst\|firmware_ROM:the_firmware_ROM\|altsyncram:the_altsyncram\|altsyncram_gq01:auto_generated " "Info: Elaborating entity \"altsyncram_gq01\" for hierarchy \"rcIII:inst\|firmware_ROM:the_firmware_ROM\|altsyncram:the_altsyncram\|altsyncram_gq01:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0_avalon_jtag_slave_arbitrator rcIII:inst\|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave " "Info: Elaborating entity \"jtag_uart_0_avalon_jtag_slave_arbitrator\" for hierarchy \"rcIII:inst\|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave\"" {  } { { "rcIII.v" "the_jtag_uart_0_avalon_jtag_slave" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3391 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1603) " "Warning: Verilog HDL assignment warning at rcIII.v(1603): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1603 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1604) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1604): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1604 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(1624) " "Warning: Verilog HDL assignment warning at rcIII.v(1624): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1624 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(1627) " "Warning: Verilog HDL assignment warning at rcIII.v(1627): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1627 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(1642) " "Warning: Verilog HDL assignment warning at rcIII.v(1642): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1642 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1652) " "Warning: Verilog HDL assignment warning at rcIII.v(1652): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1652 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1662) " "Warning: Verilog HDL assignment warning at rcIII.v(1662): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1662 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1665) " "Warning: Verilog HDL assignment warning at rcIII.v(1665): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1665 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1678) " "Warning: Verilog HDL assignment warning at rcIII.v(1678): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1678 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1681) " "Warning: Verilog HDL assignment warning at rcIII.v(1681): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1681 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1684) " "Warning: Verilog HDL assignment warning at rcIII.v(1684): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1684 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "25 1 rcIII.v(1706) " "Warning: Verilog HDL assignment warning at rcIII.v(1706): truncated value with size 25 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1706 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1712) " "Warning: Verilog HDL assignment warning at rcIII.v(1712): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1712 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1713) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1713): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1713 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1736) " "Warning: Verilog HDL assignment warning at rcIII.v(1736): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1736 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave rcIII.v(1531) " "Warning: Output port \"cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave\" at rcIII.v(1531) has no driver" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1531 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "jtag_uart_0.v 7 7 " "Info: Using design file jtag_uart_0.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 jtag_uart_0_log_module " "Info: Found entity 1: jtag_uart_0_log_module" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 jtag_uart_0_sim_scfifo_w " "Info: Found entity 2: jtag_uart_0_sim_scfifo_w" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 jtag_uart_0_scfifo_w " "Info: Found entity 3: jtag_uart_0_scfifo_w" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 105 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 jtag_uart_0_drom_module " "Info: Found entity 4: jtag_uart_0_drom_module" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 179 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_0_sim_scfifo_r " "Info: Found entity 5: jtag_uart_0_sim_scfifo_r" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 323 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_0_scfifo_r " "Info: Found entity 6: jtag_uart_0_scfifo_r" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 403 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 jtag_uart_0 " "Info: Found entity 7: jtag_uart_0" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 479 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0 rcIII:inst\|jtag_uart_0:the_jtag_uart_0 " "Info: Elaborating entity \"jtag_uart_0\" for hierarchy \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\"" {  } { { "rcIII.v" "the_jtag_uart_0" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3407 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 jtag_uart_0.v(662) " "Warning: Verilog HDL assignment warning at jtag_uart_0.v(662): truncated value with size 32 to match size of target (1)" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 662 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "jtag_uart_0.v(663) " "Warning: (10037) Verilog HDL or VHDL warning at jtag_uart_0.v(663): condition expression evaluates to a constant" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 663 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 jtag_uart_0.v(713) " "Warning: Verilog HDL assignment warning at jtag_uart_0.v(713): truncated value with size 32 to match size of target (1)" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 713 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "jtag_uart_0.v(714) " "Warning: (10037) Verilog HDL or VHDL warning at jtag_uart_0.v(714): condition expression evaluates to a constant" {  } { { "jtag_uart_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 714 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0_scfifo_w rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w " "Info: Elaborating entity \"jtag_uart_0_scfifo_w\" for hierarchy \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\"" {  } { { "jtag_uart_0.v" "the_jtag_uart_0_scfifo_w" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 559 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../quartus50/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../quartus50/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/scfifo.tdf" 234 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Info: Elaborating entity \"scfifo\" for hierarchy \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart_0.v" "wfifo" { Text "C:/altera/kits/nios2/components/rcIII/system/jtag_uart_0.v" 161 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_j4p.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_j4p.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_j4p " "Info: Found entity 1: scfifo_j4p" {  } { { "db/scfifo_j4p.tdf" "" { Text "C:/altera/kits/nios2/components/rcIII/system/db/scfifo_j4p.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_j4p rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_j4p:auto_generated " "Info: Elaborating entity \"scfifo_j4p\" for hierarchy \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_j4p:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/scfifo.tdf" 294 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_qap.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_qap.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_qap " "Info: Found entity 1: a_dpfifo_qap" {  } { { "db/a_dpfifo_qap.tdf" "" { Text "C:/altera/kits/nios2/components/rcIII/system/db/a_dpfifo_qap.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_qap rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_j4p:auto_generated\|a_dpfifo_qap:dpfifo " "Info: Elaborating entity \"a_dpfifo_qap\" for hierarchy \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_j4p:auto_generated\|a_dpfifo_qap:dpfifo\"" {  } { { "db/scfifo_j4p.tdf" "dpfifo" { Text "C:/altera/kits/nios2/components/rcIII/system/db/scfifo_j4p.tdf" 36 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Info: Found entity 1: a_fefifo_7cf" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/altera/kits/nios2/components/rcIII/system/db/a_fefifo_7cf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_j4p:auto_generated\|a_dpfifo_qap:dpfifo\|a_fefifo_7cf:fifo_state " "Info: Elaborating entity \"a_fefifo_7cf\" for hierarchy \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_j4p:auto_generated\|a_dpfifo_qap:dpfifo\|a_fefifo_7cf:fifo_state\"" {  } { { "db/a_dpfifo_qap.tdf" "fifo_state" { Text "C:/altera/kits/nios2/components/rcIII/system/db/a_dpfifo_qap.tdf" 41 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rj7.tdf 1 1 " "Info: Found 1 design uni