rciii.map.qmsg

niosII基础上实现的嵌入式网络驱动

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1056) " "Warning: Verilog HDL assignment warning at rcIII.v(1056): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1056 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 rcIII.v(1058) " "Warning: Verilog HDL assignment warning at rcIII.v(1058): truncated value with size 32 to match size of target (4)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1058 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "data_RAM.v 1 1 " "Info: Using design file data_RAM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 data_RAM " "Info: Found entity 1: data_RAM" {  } { { "data_RAM.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/data_RAM.v" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_RAM rcIII:inst\|data_RAM:the_data_RAM " "Info: Elaborating entity \"data_RAM\" for hierarchy \"rcIII:inst\|data_RAM:the_data_RAM\"" {  } { { "rcIII.v" "the_data_RAM" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3314 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rcIII:inst\|data_RAM:the_data_RAM\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rcIII:inst\|data_RAM:the_data_RAM\|altsyncram:the_altsyncram\"" {  } { { "data_RAM.v" "the_altsyncram" { Text "C:/altera/kits/nios2/components/rcIII/system/data_RAM.v" 83 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ca01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ca01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ca01 " "Info: Found entity 1: altsyncram_ca01" {  } { { "db/altsyncram_ca01.tdf" "" { Text "C:/altera/kits/nios2/components/rcIII/system/db/altsyncram_ca01.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ca01 rcIII:inst\|data_RAM:the_data_RAM\|altsyncram:the_altsyncram\|altsyncram_ca01:auto_generated " "Info: Elaborating entity \"altsyncram_ca01\" for hierarchy \"rcIII:inst\|data_RAM:the_data_RAM\|altsyncram:the_altsyncram\|altsyncram_ca01:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "firmware_ROM_s1_arbitrator rcIII:inst\|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1 " "Info: Elaborating entity \"firmware_ROM_s1_arbitrator\" for hierarchy \"rcIII:inst\|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1\"" {  } { { "rcIII.v" "the_firmware_ROM_s1" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3346 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1221) " "Warning: Verilog HDL assignment warning at rcIII.v(1221): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1221 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1222) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1222): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1222 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(1236) " "Warning: Verilog HDL assignment warning at rcIII.v(1236): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1236 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(1239) " "Warning: Verilog HDL assignment warning at rcIII.v(1239): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1239 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(1257) " "Warning: Verilog HDL assignment warning at rcIII.v(1257): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1257 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1267) " "Warning: Verilog HDL assignment warning at rcIII.v(1267): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1267 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1283) " "Warning: Verilog HDL assignment warning at rcIII.v(1283): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1283 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1284) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1284): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1284 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1285) " "Warning: Verilog HDL assignment warning at rcIII.v(1285): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1285 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 rcIII.v(1301) " "Warning: Verilog HDL assignment warning at rcIII.v(1301): truncated value with size 2 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1301 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1307) " "Warning: Verilog HDL assignment warning at rcIII.v(1307): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1307 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1308) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1308): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1308 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1327) " "Warning: Verilog HDL assignment warning at rcIII.v(1327): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1327 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1328) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1328): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1328 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1329) " "Warning: Verilog HDL assignment warning at rcIII.v(1329): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1329 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 rcIII.v(1341) " "Warning: Verilog HDL assignment warning at rcIII.v(1341): truncated value with size 2 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1341 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1347) " "Warning: Verilog HDL assignment warning at rcIII.v(1347): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1347 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1348) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1348): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1348 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(1387) " "Warning: Verilog HDL assignment warning at rcIII.v(1387): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1387 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(1398) " "Warning: Verilog HDL assignment warning at rcIII.v(1398): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1398 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(1404) " "Warning: Verilog HDL assignment warning at rcIII.v(1404): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1404 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "25 10 rcIII.v(1424) " "Warning: Verilog HDL assignment warning at rcIII.v(1424): truncated value with size 25 to match size of target (10)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1424 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1431) " "Warning: Verilog HDL assignment warning at rcIII.v(1431): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1431 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1432) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1432): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1432 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1438) " "Warning: Verilog HDL assignment warning at rcIII.v(1438): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1438 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1447) " "Warning: Verilog HDL assignment warning at rcIII.v(1447): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1447 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1455) " "Warning: Verilog HDL assignment warning at rcIII.v(1455): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1455 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 rcIII.v(1457) " "Warning: Verilog HDL assignment warning at rcIII.v(1457): truncated value with size 32 to match size of target (4)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1457 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "firmware_ROM.v 1 1 " "Info: Using design file firmware_ROM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 firmware_ROM " "Info: Found entity 1: firmware_ROM" {  } { { "firmware_ROM.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/firmware_ROM.v" 16 -1 0 } }  } 0}  } {  } 0}