divide.tan.rpt

用VHDL开发的数字钟资料 完整的实验代码

; N/A                                     ; 56.50 MHz ( period = 17.700 ns )                    ; c1[16] ; c1[11] ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 56.50 MHz ( period = 17.700 ns )                    ; c1[4]  ; c1[15] ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 56.50 MHz ( period = 17.700 ns )                    ; c1[16] ; c1[15] ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 56.50 MHz ( period = 17.700 ns )                    ; c1[4]  ; c1[16] ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 56.50 MHz ( period = 17.700 ns )                    ; c1[16] ; c1[16] ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 56.82 MHz ( period = 17.600 ns )                    ; c1[13] ; out1   ; clk        ; clk      ; None                        ; None                      ; 14.000 ns               ;
; N/A                                     ; 57.80 MHz ( period = 17.300 ns )                    ; c1[1]  ; out1   ; clk        ; clk      ; None                        ; None                      ; 13.700 ns               ;
; N/A                                     ; 57.80 MHz ( period = 17.300 ns )                    ; c1[4]  ; c1[18] ; clk        ; clk      ; None                        ; None                      ; 13.700 ns               ;
; N/A                                     ; 58.48 MHz ( period = 17.100 ns )                    ; c1[12] ; out1   ; clk        ; clk      ; None                        ; None                      ; 13.500 ns               ;
; N/A                                     ; 58.82 MHz ( period = 17.000 ns )                    ; c1[3]  ; out1   ; clk        ; clk      ; None                        ; None                      ; 13.400 ns               ;
; N/A                                     ; 58.82 MHz ( period = 17.000 ns )                    ; c1[4]  ; c1[17] ; clk        ; clk      ; None                        ; None                      ; 13.400 ns               ;
; N/A                                     ; 58.82 MHz ( period = 17.000 ns )                    ; c1[2]  ; c1[14] ; clk        ; clk      ; None                        ; None                      ; 13.400 ns               ;
; N/A                                     ; 59.17 MHz ( period = 16.900 ns )                    ; c1[6]  ; out1   ; clk        ; clk      ; None                        ; None                      ; 13.300 ns               ;
; N/A                                     ; 59.17 MHz ( period = 16.900 ns )                    ; c1[1]  ; c1[14] ; clk        ; clk      ; None                        ; None                      ; 13.300 ns               ;
; N/A                                     ; 59.52 MHz ( period = 16.800 ns )                    ; c1[0]  ; c1[18] ; clk        ; clk      ; None                        ; None                      ; 13.200 ns               ;
; N/A                                     ; 59.52 MHz ( period = 16.800 ns )                    ; c1[2]  ; c1[11] ; clk        ; clk      ; None                        ; None                      ; 13.200 ns               ;
; N/A                                     ; 60.24 MHz ( period = 16.600 ns )                    ; c1[17] ; c1[11] ; clk        ; clk      ; None                        ; None                      ; 13.000 ns               ;
; N/A                                     ; 60.24 MHz ( period = 16.600 ns )                    ; c1[17] ; c1[15] ; clk        ; clk      ; None                        ; None                      ; 13.000 ns               ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;        ;        ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To     ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A   ; None         ; 13.100 ns  ; out1 ; outclk ; clk        ;
+-------+--------------+------------+------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Wed Apr 22 19:56:37 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off divide -c divide
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 40.82 MHz between source register "c1[15]" and destination register "c1[0]" (period= 24.5 ns)
    Info: + Longest register to register delay is 20.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C5; Fanout = 6; REG Node = 'c1[15]'
        Info: 2: + IC(2.300 ns) + CELL(2.300 ns) = 4.600 ns; Loc. = LC1_C2; Fanout = 2; COMB Node = 'LessThan0~453'
        Info: 3: + IC(2.300 ns) + CELL(1.200 ns) = 8.100 ns; Loc. = LC3_C4; Fanout = 1; COMB Node = 'LessThan0~486'
        Info: 4: + IC(0.000 ns) + CELL(0.900 ns) = 9.000 ns; Loc. = LC4_C4; Fanout = 1; COMB Node = 'LessThan0~489'
        Info: 5: + IC(0.000 ns) + CELL(1.500 ns) = 10.500 ns; Loc. = LC5_C4; Fanout = 1; COMB Node = 'LessThan0~474'
        Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 12.900 ns; Loc. = LC1_C4; Fanout = 2; COMB Node = 'LessThan0~456'
        Info: 7: + IC(2.200 ns) + CELL(1.800 ns) = 16.900 ns; Loc. = LC8_C5; Fanout = 9; COMB Node = 'c1~409'
        Info: 8: + IC(2.300 ns) + CELL(1.700 ns) = 20.900 ns; Loc. = LC3_C6; Fanout = 3; REG Node = 'c1[0]'
        Info: Total cell delay = 11.200 ns ( 53.59 % )
        Info: Total interconnect delay = 9.700 ns ( 46.41 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C6; Fanout = 3; REG Node = 'c1[0]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "clk" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C5; Fanout = 6; REG Node = 'c1[15]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "clk" to destination pin "outclk" through register "out1" is 13.100 ns
    Info: + Longest clock path from clock "clk" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_C5; Fanout = 2; REG Node = 'out1'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C5; Fanout = 2; REG Node = 'out1'
        Info: 2: + IC(1.600 ns) + CELL(5.100 ns) = 6.700 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'outclk'
        Info: Total cell delay = 5.100 ns ( 76.12 % )
        Info: Total interconnect delay = 1.600 ns ( 23.88 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Wed Apr 22 19:56:40 2009
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:01