divide.map.summary

用VHDL开发的数字钟资料 完整的实验代码

Analysis & Synthesis Status : Successful - Wed Apr 22 19:56:10 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : divide
Top-level Entity Name : divide
Family : FLEX10K
Total logic elements : 61
Total pins : 2
Total memory bits : 0