prev_cmp_led.qmsg

来自「用VHDL开发的数字钟资料 完整的实验代码」· QMSG 代码 · 共 127 行 · 第 1/5 页

{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "b1\[4\] " "Warning: Latch b1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA s1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal s1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c\[4\] " "Warning: Latch c\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c1\[4\] " "Warning: Latch c1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal m1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 12 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "d\[4\] " "Warning: Latch d\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA h\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal h\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 13 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "d1\[4\] " "Warning: Latch d1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA h1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal h1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "b\[5\] " "Warning: Latch b\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA s\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal s\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "b1\[5\] " "Warning: Latch b1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA s1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal s1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c\[5\] " "Warning: Latch c\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c1\[5\] " "Warning: Latch c1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal m1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 12 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "d\[5\] " "Warning: Latch d\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA h\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal h\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 13 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "d1\[5\] " "Warning: Latch d1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA h1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal h1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "b\[6\] " "Warning: Latch b\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA s\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal s\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "b1\[6\] " "Warning: Latch b1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA s1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal s1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c\[6\] " "Warning: Latch c\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c1\[6\] " "Warning: Latch c1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal m1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 12 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "d\[6\] " "Warning: Latch d\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA h\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal h\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 13 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "d1\[6\] " "Warning: Latch d1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA h1\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal h1\[1\]" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "154 " "Info: Implemented 154 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Info: Implemented 25 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "119 " "Info: Implemented 119 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 90 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 90 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Info: Peak virtual memory: 172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 22:19:42 2009 " "Info: Processing ended: Wed Apr 22 22:19:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 22 22:19:44 2009 " "Info: Processing started: Wed Apr 22 22:19:44 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off led -c led " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led -c led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "led EPF10K10LC84-4 " "Info: Selected device EPF10K10LC84-4 for design \"led\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 0}