led.map.rpt

用VHDL开发的数字钟资料 完整的实验代码

; d1[4]                                               ; Mux48               ; yes                    ;
; b[5]                                                ; Mux9                ; yes                    ;
; b1[5]                                               ; Mux16               ; yes                    ;
; c[5]                                                ; Mux24               ; yes                    ;
; c1[5]                                               ; Mux32               ; yes                    ;
; d[5]                                                ; Mux40               ; yes                    ;
; d1[5]                                               ; Mux48               ; yes                    ;
; b[6]                                                ; Mux9                ; yes                    ;
; b1[6]                                               ; Mux16               ; yes                    ;
; c[6]                                                ; Mux24               ; yes                    ;
; c1[6]                                               ; Mux32               ; yes                    ;
; d[6]                                                ; Mux40               ; yes                    ;
; d1[6]                                               ; Mux48               ; yes                    ;
; Number of user-specified and inferred latches = 42  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Wed Apr 22 22:19:38 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led
Info: Found 2 design units, including 1 entities, in source file led.vhd
    Info: Found design unit 1: led-one
    Info: Found entity 1: led
Info: Elaborating entity "led" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at led.vhd(48): inferring latch(es) for signal or variable "d1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(48): inferring latch(es) for signal or variable "d", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(77): inferring latch(es) for signal or variable "c1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(77): inferring latch(es) for signal or variable "c", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(106): inferring latch(es) for signal or variable "b1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at led.vhd(106): inferring latch(es) for signal or variable "b", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "b[0]" at led.vhd(106)
Info (10041): Inferred latch for "b[1]" at led.vhd(106)
Info (10041): Inferred latch for "b[2]" at led.vhd(106)
Info (10041): Inferred latch for "b[3]" at led.vhd(106)
Info (10041): Inferred latch for "b[4]" at led.vhd(106)
Info (10041): Inferred latch for "b[5]" at led.vhd(106)
Info (10041): Inferred latch for "b[6]" at led.vhd(106)
Info (10041): Inferred latch for "b1[0]" at led.vhd(106)
Info (10041): Inferred latch for "b1[1]" at led.vhd(106)
Info (10041): Inferred latch for "b1[2]" at led.vhd(106)
Info (10041): Inferred latch for "b1[3]" at led.vhd(106)
Info (10041): Inferred latch for "b1[4]" at led.vhd(106)
Info (10041): Inferred latch for "b1[5]" at led.vhd(106)
Info (10041): Inferred latch for "b1[6]" at led.vhd(106)
Info (10041): Inferred latch for "c[0]" at led.vhd(77)
Info (10041): Inferred latch for "c[1]" at led.vhd(77)
Info (10041): Inferred latch for "c[2]" at led.vhd(77)
Info (10041): Inferred latch for "c[3]" at led.vhd(77)
Info (10041): Inferred latch for "c[4]" at led.vhd(77)
Info (10041): Inferred latch for "c[5]" at led.vhd(77)
Info (10041): Inferred latch for "c[6]" at led.vhd(77)
Info (10041): Inferred latch for "c1[0]" at led.vhd(77)
Info (10041): Inferred latch for "c1[1]" at led.vhd(77)
Info (10041): Inferred latch for "c1[2]" at led.vhd(77)
Info (10041): Inferred latch for "c1[3]" at led.vhd(77)
Info (10041): Inferred latch for "c1[4]" at led.vhd(77)
Info (10041): Inferred latch for "c1[5]" at led.vhd(77)
Info (10041): Inferred latch for "c1[6]" at led.vhd(77)
Info (10041): Inferred latch for "d[0]" at led.vhd(48)
Info (10041): Inferred latch for "d[1]" at led.vhd(48)
Info (10041): Inferred latch for "d[2]" at led.vhd(48)
Info (10041): Inferred latch for "d[3]" at led.vhd(48)
Info (10041): Inferred latch for "d[4]" at led.vhd(48)
Info (10041): Inferred latch for "d[5]" at led.vhd(48)
Info (10041): Inferred latch for "d[6]" at led.vhd(48)
Info (10041): Inferred latch for "d1[0]" at led.vhd(48)
Info (10041): Inferred latch for "d1[1]" at led.vhd(48)
Info (10041): Inferred latch for "d1[2]" at led.vhd(48)
Info (10041): Inferred latch for "d1[3]" at led.vhd(48)
Info (10041): Inferred latch for "d1[4]" at led.vhd(48)
Info (10041): Inferred latch for "d1[5]" at led.vhd(48)
Info (10041): Inferred latch for "d1[6]" at led.vhd(48)
Warning: Latch b[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[1]
Warning: Latch b1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[1]
Warning: Latch c[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch c1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[1]
Warning: Latch d[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[1]
Warning: Latch d1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[1]
Warning: Latch b[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[2]
Warning: Latch b1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[2]
Warning: Latch c[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch c1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[2]
Warning: Latch d[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[2]
Warning: Latch d1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[2]
Warning: Latch b[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[1]
Warning: Latch b1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[1]
Warning: Latch c[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch c1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[1]
Warning: Latch d[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[1]
Warning: Latch d1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[1]
Warning: Latch b[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[1]
Warning: Latch b1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[1]
Warning: Latch c[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch c1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[1]
Warning: Latch d[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[1]
Warning: Latch d1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[1]
Warning: Latch b[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[1]
Warning: Latch b1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[1]
Warning: Latch c[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch c1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[1]
Warning: Latch d[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[1]
Warning: Latch d1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[1]
Warning: Latch b[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[1]
Warning: Latch b1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[1]
Warning: Latch c[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch c1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[1]
Warning: Latch d[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[1]
Warning: Latch d1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[1]
Warning: Latch b[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s[1]
Warning: Latch b1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal s1[1]
Warning: Latch c[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch c1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m1[1]
Warning: Latch d[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h[1]
Warning: Latch d1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal h1[1]
Info: Implemented 154 device resources after synthesis - the final resource count might be different
    Info: Implemented 25 input pins
    Info: Implemented 10 output pins
    Info: Implemented 119 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 90 warnings
    Info: Peak virtual memory: 172 megabytes
    Info: Processing ended: Wed Apr 22 22:19:42 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:02