prev_cmp_clock.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[2\] " "Warning: Latch led:u3\|b1\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[2\] " "Warning: Latch led:u3\|c\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[2\] " "Warning: Latch led:u3\|c1\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[2\] " "Warning: Latch led:u3\|d\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[2\] " "Warning: Latch led:u3\|d1\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[3\] " "Warning: Latch led:u3\|b\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[3\] " "Warning: Latch led:u3\|b1\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[3\] " "Warning: Latch led:u3\|c\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[3\] " "Warning: Latch led:u3\|c1\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[3\] " "Warning: Latch led:u3\|d\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[3\] " "Warning: Latch led:u3\|d1\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[4\] " "Warning: Latch led:u3\|b\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[4\] " "Warning: Latch led:u3\|b1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[4\] " "Warning: Latch led:u3\|c\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[4\] " "Warning: Latch led:u3\|c1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[4\] " "Warning: Latch led:u3\|d\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[4\] " "Warning: Latch led:u3\|d1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[5\] " "Warning: Latch led:u3\|b\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[5\] " "Warning: Latch led:u3\|b1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[5\] " "Warning: Latch led:u3\|c\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[5\] " "Warning: Latch led:u3\|c1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[5\] " "Warning: Latch led:u3\|d\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[5\] " "Warning: Latch led:u3\|d1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[6\] " "Warning: Latch led:u3\|b\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[6\] " "Warning: Latch led:u3\|b1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[6\] " "Warning: Latch led:u3\|c\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[6\] " "Warning: Latch led:u3\|c1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[6\] " "Warning: Latch led:u3\|d\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[6\] " "Warning: Latch led:u3\|d1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}