prev_cmp_clock.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[5\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[5\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[6\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[6\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "divide:u1\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"divide:u1\|Add0\"" {  } { { "divide.vhd" "Add0" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "time:u2\|Add4 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"time:u2\|Add4\"" {  } { { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add4" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "divide:u1\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"divide:u1\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 20 " "Info: Parameter \"LPM_WIDTH\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|addcore:adder divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "time:u2\|lpm_add_sub:Add4 " "Info: Elaborated megafunction instantiation \"time:u2\|lpm_add_sub:Add4\"" {  } { { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "time:u2\|lpm_add_sub:Add4 " "Info: Instantiated megafunction \"time:u2\|lpm_add_sub:Add4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "time:u2\|lpm_add_sub:Add4\|addcore:adder time:u2\|lpm_add_sub:Add4 " "Info: Elaborated megafunction instantiation \"time:u2\|lpm_add_sub:Add4\|addcore:adder\", which is child of megafunction instantiation \"time:u2\|lpm_add_sub:Add4\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "time:u2\|lpm_add_sub:Add4\|addcore:adder\|a_csnbuffer:oflow_node time:u2\|lpm_add_sub:Add4 " "Info: Elaborated megafunction instantiation \"time:u2\|lpm_add_sub:Add4\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"time:u2\|lpm_add_sub:Add4\"" {  } { { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "time:u2\|lpm_add_sub:Add4\|addcore:adder\|a_csnbuffer:result_node time:u2\|lpm_add_sub:Add4 " "Info: Elaborated megafunction instantiation \"time:u2\|lpm_add_sub:Add4\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"time:u2\|lpm_add_sub:Add4\"" {  } { { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "time:u2\|lpm_add_sub:Add4\|altshift:result_ext_latency_ffs time:u2\|lpm_add_sub:Add4 " "Info: Elaborated megafunction instantiation \"time:u2\|lpm_add_sub:Add4\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"time:u2\|lpm_add_sub:Add4\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[0\] " "Warning: Latch led:u3\|b\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[0\] " "Warning: Latch led:u3\|b1\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[0\] " "Warning: Latch led:u3\|c\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[0\] " "Warning: Latch led:u3\|c1\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[0\] " "Warning: Latch led:u3\|d\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[0\] " "Warning: Latch led:u3\|d1\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[1\] " "Warning: Latch led:u3\|b\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[2\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b1\[1\] " "Warning: Latch led:u3\|b1\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|b\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|b\[2\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c\[1\] " "Warning: Latch led:u3\|c\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|c\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|c\[2\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|c1\[1\] " "Warning: Latch led:u3\|c1\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|d\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|d\[2\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d\[1\] " "Warning: Latch led:u3\|d\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|e\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|e\[2\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|d1\[1\] " "Warning: Latch led:u3\|d1\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|f\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|f\[2\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "led:u3\|b\[2\] " "Warning: Latch led:u3\|b\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA time:u2\|a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal time:u2\|a\[1\]" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}