clock.fnsim.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[1\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[1\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[2\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[2\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[3\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[3\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[4\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[4\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[5\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[5\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[6\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[6\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[0\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[0\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[1\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[1\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[2\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[2\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[3\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[3\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[4\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[4\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[5\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[5\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c1\[6\] led.vhd(77) " "Info (10041): Inferred latch for \"c1\[6\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[0\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[0\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[1\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[1\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[2\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[2\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[3\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[3\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[4\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[4\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[5\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[5\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d\[6\] led.vhd(48) " "Info (10041): Inferred latch for \"d\[6\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[0\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[0\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[1\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[1\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[2\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[2\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[3\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[3\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[4\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[4\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[5\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[5\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "d1\[6\] led.vhd(48) " "Info (10041): Inferred latch for \"d1\[6\]\" at led.vhd(48)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "divide:u1\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"divide:u1\|Add0\"" {  } { { "divide.vhd" "Add0" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "divide:u1\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"divide:u1\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 20 " "Info: Parameter \"LPM_WIDTH\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|addcore:adder divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide:u1\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs divide:u1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"divide:u1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 13 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "177 " "Info: Peak virtual memory: 177 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 20:20:40 2009 " "Info: Processing ended: Wed Apr 22 20:20:40 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}