prev_cmp_clock.tan.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[0\] " "Warning: Node \"led:u3\|c\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[0\] " "Warning: Node \"led:u3\|b1\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[1\] " "Warning: Node \"led:u3\|c\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[1\] " "Warning: Node \"led:u3\|b1\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[2\] " "Warning: Node \"led:u3\|c\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[2\] " "Warning: Node \"led:u3\|b1\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[3\] " "Warning: Node \"led:u3\|c\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[3\] " "Warning: Node \"led:u3\|b1\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[4\] " "Warning: Node \"led:u3\|c\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[4\] " "Warning: Node \"led:u3\|b1\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[5\] " "Warning: Node \"led:u3\|c\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[5\] " "Warning: Node \"led:u3\|b1\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[6\] " "Warning: Node \"led:u3\|b\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[6\] " "Warning: Node \"led:u3\|c1\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b1\[6\] " "Warning: Node \"led:u3\|b1\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[6\] " "Warning: Node \"led:u3\|d1\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c\[6\] " "Warning: Node \"led:u3\|c\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[6\] " "Warning: Node \"led:u3\|d\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[0\] " "Warning: Node \"led:u3\|d1\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[0\] " "Warning: Node \"led:u3\|d\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[0\] " "Warning: Node \"led:u3\|c1\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[0\] " "Warning: Node \"led:u3\|b\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[1\] " "Warning: Node \"led:u3\|d1\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[1\] " "Warning: Node \"led:u3\|d\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[1\] " "Warning: Node \"led:u3\|c1\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[1\] " "Warning: Node \"led:u3\|b\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[2\] " "Warning: Node \"led:u3\|d1\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[2\] " "Warning: Node \"led:u3\|d\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[2\] " "Warning: Node \"led:u3\|c1\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[2\] " "Warning: Node \"led:u3\|b\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[3\] " "Warning: Node \"led:u3\|d1\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[3\] " "Warning: Node \"led:u3\|d\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[3\] " "Warning: Node \"led:u3\|c1\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[3\] " "Warning: Node \"led:u3\|b\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[4\] " "Warning: Node \"led:u3\|d1\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[4\] " "Warning: Node \"led:u3\|d\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[4\] " "Warning: Node \"led:u3\|c1\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[4\] " "Warning: Node \"led:u3\|b\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d1\[5\] " "Warning: Node \"led:u3\|d1\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|d\[5\] " "Warning: Node \"led:u3\|d\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|c1\[5\] " "Warning: Node \"led:u3\|c1\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "led:u3\|b\[5\] " "Warning: Node \"led:u3\|b\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk0 " "Info: Assuming node \"clk0\" is an undefined clock" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 6 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 7 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "27 " "Warning: Found 27 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "led:u3\|Mux40~33 " "Info: Detected gated clock \"led:u3\|Mux40~33\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 63 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "led:u3\|Mux40~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|e\[3\] " "Info: Detected ripple clock \"time:u2\|e\[3\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|e\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|e\[2\] " "Info: Detected ripple clock \"time:u2\|e\[2\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|e\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|e\[1\] " "Info: Detected ripple clock \"time:u2\|e\[1\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|e\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "led:u3\|Mux48~37 " "Info: Detected gated clock \"led:u3\|Mux48~37\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 50 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "led:u3\|Mux48~37" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|f\[3\] " "Info: Detected ripple clock \"time:u2\|f\[3\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|f\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|f\[2\] " "Info: Detected ripple clock \"time:u2\|f\[2\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|f\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|f\[1\] " "Info: Detected ripple clock \"time:u2\|f\[1\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 59 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|f\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|chour " "Info: Detected ripple clock \"time:u2\|chour\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 21 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|chour" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "led:u3\|Mux9~32 " "Info: Detected gated clock \"led:u3\|Mux9~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 121 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "led:u3\|Mux9~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|a\[2\] " "Info: Detected ripple clock \"time:u2\|a\[2\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|a\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|a\[1\] " "Info: Detected ripple clock \"time:u2\|a\[1\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|a\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "led:u3\|Mux32~32 " "Info: Detected gated clock \"led:u3\|Mux32~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 79 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "led:u3\|Mux32~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|d\[3\] " "Info: Detected ripple clock \"time:u2\|d\[3\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|d\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|d\[2\] " "Info: Detected ripple clock \"time:u2\|d\[2\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|d\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|d\[1\] " "Info: Detected ripple clock \"time:u2\|d\[1\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|d\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "led:u3\|Mux24~32 " "Info: Detected gated clock \"led:u3\|Mux24~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 92 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "led:u3\|Mux24~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|c\[3\] " "Info: Detected ripple clock \"time:u2\|c\[3\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|c\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|c\[2\] " "Info: Detected ripple clock \"time:u2\|c\[2\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|c\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|c\[1\] " "Info: Detected ripple clock \"time:u2\|c\[1\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|c\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|cmin " "Info: Detected ripple clock \"time:u2\|cmin\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 20 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|cmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "led:u3\|Mux16~32 " "Info: Detected gated clock \"led:u3\|Mux16~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 108 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "led:u3\|Mux16~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|b\[3\] " "Info: Detected ripple clock \"time:u2\|b\[3\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|b\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|a\[3\] " "Info: Detected ripple clock \"time:u2\|a\[3\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|a\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|b\[2\] " "Info: Detected ripple clock \"time:u2\|b\[2\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|b\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "time:u2\|b\[1\] " "Info: Detected ripple clock \"time:u2\|b\[1\]\" as buffer" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "time:u2\|b\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide:u1\|out1 " "Info: Detected ripple clock \"divide:u1\|out1\" as buffer" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "divide:u1\|out1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}