clock.tan.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "time:u2\|c\[3\] led:u3\|c\[0\] clk0 4.8 ns " "Info: Found hold time violation between source  pin or register \"time:u2\|c\[3\]\" and destination pin or register \"led:u3\|c\[0\]\" for clock \"clk0\" (Hold time is 4.8 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "11.200 ns + Largest " "Info: + Largest clock skew is 11.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 32.000 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to destination register is 32.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk0 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.100 ns) + CELL(1.100 ns) 11.700 ns divide:u1\|out1 2 REG LC1_A14 11 " "Info: 2: + IC(7.100 ns) + CELL(1.100 ns) = 11.700 ns; Loc. = LC1_A14; Fanout = 11; REG Node = 'divide:u1\|out1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk0 divide:u1|out1 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 17.400 ns time:u2\|cmin 3 REG LC8_B9 10 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 17.400 ns; Loc. = LC8_B9; Fanout = 10; REG Node = 'time:u2\|cmin'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { divide:u1|out1 time:u2|cmin } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.100 ns) 21.900 ns time:u2\|c\[2\] 4 REG LC3_C10 12 " "Info: 4: + IC(3.400 ns) + CELL(1.100 ns) = 21.900 ns; Loc. = LC3_C10; Fanout = 12; REG Node = 'time:u2\|c\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { time:u2|cmin time:u2|c[2] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(2.300 ns) 26.700 ns led:u3\|Mux24~32 5 COMB LC1_C1 7 " "Info: 5: + IC(2.500 ns) + CELL(2.300 ns) = 26.700 ns; Loc. = LC1_C1; Fanout = 7; COMB Node = 'led:u3\|Mux24~32'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { time:u2|c[2] led:u3|Mux24~32 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.300 ns) 32.000 ns led:u3\|c\[0\] 6 REG LC5_C9 1 " "Info: 6: + IC(3.000 ns) + CELL(2.300 ns) = 32.000 ns; Loc. = LC5_C9; Fanout = 1; REG Node = 'led:u3\|c\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { led:u3|Mux24~32 led:u3|c[0] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.400 ns ( 35.63 % ) " "Info: Total cell delay = 11.400 ns ( 35.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "20.600 ns ( 64.38 % ) " "Info: Total interconnect delay = 20.600 ns ( 64.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "32.000 ns" { clk0 divide:u1|out1 time:u2|cmin time:u2|c[2] led:u3|Mux24~32 led:u3|c[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "32.000 ns" { clk0 {} clk0~out {} divide:u1|out1 {} time:u2|cmin {} time:u2|c[2] {} led:u3|Mux24~32 {} led:u3|c[0] {} } { 0.000ns 0.000ns 7.100ns 4.600ns 3.400ns 2.500ns 3.000ns } { 0.000ns 3.500ns 1.100ns 1.100ns 1.100ns 2.300ns 2.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 20.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clk0\" to source register is 20.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk0 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.100 ns) + CELL(1.100 ns) 11.700 ns divide:u1\|out1 2 REG LC1_A14 11 " "Info: 2: + IC(7.100 ns) + CELL(1.100 ns) = 11.700 ns; Loc. = LC1_A14; Fanout = 11; REG Node = 'divide:u1\|out1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk0 divide:u1|out1 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 17.400 ns time:u2\|cmin 3 REG LC8_B9 10 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 17.400 ns; Loc. = LC8_B9; Fanout = 10; REG Node = 'time:u2\|cmin'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { divide:u1|out1 time:u2|cmin } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 20.800 ns time:u2\|c\[3\] 4 REG LC1_C9 9 " "Info: 4: + IC(3.400 ns) + CELL(0.000 ns) = 20.800 ns; Loc. = LC1_C9; Fanout = 9; REG Node = 'time:u2\|c\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { time:u2|cmin time:u2|c[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 27.40 % ) " "Info: Total cell delay = 5.700 ns ( 27.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.100 ns ( 72.60 % ) " "Info: Total interconnect delay = 15.100 ns ( 72.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "20.800 ns" { clk0 divide:u1|out1 time:u2|cmin time:u2|c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "20.800 ns" { clk0 {} clk0~out {} divide:u1|out1 {} time:u2|cmin {} time:u2|c[3] {} } { 0.000ns 0.000ns 7.100ns 4.600ns 3.400ns } { 0.000ns 3.500ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "32.000 ns" { clk0 divide:u1|out1 time:u2|cmin time:u2|c[2] led:u3|Mux24~32 led:u3|c[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "32.000 ns" { clk0 {} clk0~out {} divide:u1|out1 {} time:u2|cmin {} time:u2|c[2] {} led:u3|Mux24~32 {} led:u3|c[0] {} } { 0.000ns 0.000ns 7.100ns 4.600ns 3.400ns 2.500ns 3.000ns } { 0.000ns 3.500ns 1.100ns 1.100ns 1.100ns 2.300ns 2.300ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "20.800 ns" { clk0 divide:u1|out1 time:u2|cmin time:u2|c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "20.800 ns" { clk0 {} clk0~out {} divide:u1|out1 {} time:u2|cmin {} time:u2|c[3] {} } { 0.000ns 0.000ns 7.100ns 4.600ns 3.400ns } { 0.000ns 3.500ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns - Shortest register register " "Info: - Shortest register to register delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time:u2\|c\[3\] 1 REG LC1_C9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C9; Fanout = 9; REG Node = 'time:u2\|c\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { time:u2|c[3] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns led:u3\|Mux23~9 2 COMB LC4_C9 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC4_C9; Fanout = 1; COMB Node = 'led:u3\|Mux23~9'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { time:u2|c[3] led:u3|Mux23~9 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 5.300 ns led:u3\|c\[0\] 3 REG LC5_C9 1 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC5_C9; Fanout = 1; REG Node = 'led:u3\|c\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { led:u3|Mux23~9 led:u3|c[0] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns ( 77.36 % ) " "Info: Total cell delay = 4.100 ns ( 77.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 22.64 % ) " "Info: Total interconnect delay = 1.200 ns ( 22.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { time:u2|c[3] led:u3|Mux23~9 led:u3|c[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { time:u2|c[3] {} led:u3|Mux23~9 {} led:u3|c[0] {} } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 45 -1 0 } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 23 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "32.000 ns" { clk0 divide:u1|out1 time:u2|cmin time:u2|c[2] led:u3|Mux24~32 led:u3|c[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "32.000 ns" { clk0 {} clk0~out {} divide:u1|out1 {} time:u2|cmin {} time:u2|c[2] {} led:u3|Mux24~32 {} led:u3|c[0] {} } { 0.000ns 0.000ns 7.100ns 4.600ns 3.400ns 2.500ns 3.000ns } { 0.000ns 3.500ns 1.100ns 1.100ns 1.100ns 2.300ns 2.300ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "20.800 ns" { clk0 divide:u1|out1 time:u2|cmin time:u2|c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "20.800 ns" { clk0 {} clk0~out {} divide:u1|out1 {} time:u2|cmin {} time:u2|c[3] {} } { 0.000ns 0.000ns 7.100ns 4.600ns 3.400ns } { 0.000ns 3.500ns 1.100ns 1.100ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { time:u2|c[3] led:u3|Mux23~9 led:u3|c[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { time:u2|c[3] {} led:u3|Mux23~9 {} led:u3|c[0] {} } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.800ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "time:u2\|b\[1\] en0 clk0 2.600 ns register " "Info: tsu for register \"time:u2\|b\[1\]\" (data pin = \"en0\", clock pin = \"clk0\") is 2.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.400 ns + Longest pin register " "Info: + Longest pin to register delay is 16.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns en0 1 PIN PIN_51 12 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_51; Fanout = 12; PIN Node = 'en0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { en0 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(2.300 ns) 10.100 ns time:u2\|b\[2\]~217 2 COMB LC8_B10 4 " "Info: 2: + IC(4.300 ns) + CELL(2.300 ns) = 10.100 ns; Loc. = LC8_B10; Fanout = 4; COMB Node = 'time:u2\|b\[2\]~217'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { en0 time:u2|b[2]~217 } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 14.600 ns time:u2\|b\[3\]~218 3 COMB LC7_B9 2 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 14.600 ns; Loc. = LC7_B9; Fanout = 2; COMB Node = 'time:u2\|b\[3\]~218'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { time:u2|b[2]~217 time:u2|b[3]~218 } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 16.400 ns time:u2\|b\[1\] 4 REG LC2_B9 13 " "Info: 4: + IC(0.600 ns) + CELL(1.200 ns) = 16.400 ns; Loc. = LC2_B9; Fanout = 13; REG Node = 'time:u2\|b\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { time:u2|b[3]~218 time:u2|b[1] } "NODE_NAME" } } { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.300 ns ( 56.71 % ) " "Info: Total cell delay = 9.300 ns ( 56.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 43.29 % ) " "Info: Total interconnect delay = 7.100 ns ( 43.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.400 ns" { en0 time:u2|b[2]~217 time:u2|b[3]~218 time:u2|b[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.400 ns" { en0 {} en0~out {} time:u2|b[2]~217 {} time:u2|b[3]~218 {} time:u2|b[1] {} } { 0.000ns 0.000ns 4.300ns 2.200ns 0.600ns } { 0.000ns 3.500ns 2.300ns 2.300ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/