clock.tan.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk0 register divide:u1\|c1\[18\] register divide:u1\|c1\[5\] 35.09 MHz 28.5 ns Internal " "Info: Clock \"clk0\" has Internal fmax of 35.09 MHz between source register \"divide:u1\|c1\[18\]\" and destination register \"divide:u1\|c1\[5\]\" (period= 28.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.900 ns + Longest register register " "Info: + Longest register to register delay is 24.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divide:u1\|c1\[18\] 1 REG LC8_A19 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A19; Fanout = 7; REG Node = 'divide:u1\|c1\[18\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { divide:u1|c1[18] } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.300 ns) 5.100 ns divide:u1\|LessThan1~533 2 COMB LC3_A13 3 " "Info: 2: + IC(2.800 ns) + CELL(2.300 ns) = 5.100 ns; Loc. = LC3_A13; Fanout = 3; COMB Node = 'divide:u1\|LessThan1~533'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { divide:u1|c1[18] divide:u1|LessThan1~533 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 7.500 ns divide:u1\|LessThan1~536 3 COMB LC7_A13 1 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 7.500 ns; Loc. = LC7_A13; Fanout = 1; COMB Node = 'divide:u1\|LessThan1~536'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { divide:u1|LessThan1~533 divide:u1|LessThan1~536 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 9.900 ns divide:u1\|LessThan1~538 4 COMB LC8_A13 1 " "Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 9.900 ns; Loc. = LC8_A13; Fanout = 1; COMB Node = 'divide:u1\|LessThan1~538'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { divide:u1|LessThan1~536 divide:u1|LessThan1~538 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.800 ns divide:u1\|LessThan1~542 5 COMB LC6_A13 3 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 12.800 ns; Loc. = LC6_A13; Fanout = 3; COMB Node = 'divide:u1\|LessThan1~542'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { divide:u1|LessThan1~538 divide:u1|LessThan1~542 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 16.200 ns divide:u1\|p1~537 6 COMB LC5_A14 1 " "Info: 6: + IC(2.200 ns) + CELL(1.200 ns) = 16.200 ns; Loc. = LC5_A14; Fanout = 1; COMB Node = 'divide:u1\|p1~537'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { divide:u1|LessThan1~542 divide:u1|p1~537 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 17.700 ns divide:u1\|p1~532 7 COMB LC6_A14 2 " "Info: 7: + IC(0.000 ns) + CELL(1.500 ns) = 17.700 ns; Loc. = LC6_A14; Fanout = 2; COMB Node = 'divide:u1\|p1~532'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { divide:u1|p1~537 divide:u1|p1~532 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 20.600 ns divide:u1\|c1~374 8 COMB LC8_A14 9 " "Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 20.600 ns; Loc. = LC8_A14; Fanout = 9; COMB Node = 'divide:u1\|c1~374'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { divide:u1|p1~532 divide:u1|c1~374 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.700 ns) 24.900 ns divide:u1\|c1\[5\] 9 REG LC2_A18 5 " "Info: 9: + IC(2.600 ns) + CELL(1.700 ns) = 24.900 ns; Loc. = LC2_A18; Fanout = 5; REG Node = 'divide:u1\|c1\[5\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { divide:u1|c1~374 divide:u1|c1[5] } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.900 ns ( 59.84 % ) " "Info: Total cell delay = 14.900 ns ( 59.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.000 ns ( 40.16 % ) " "Info: Total interconnect delay = 10.000 ns ( 40.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "24.900 ns" { divide:u1|c1[18] divide:u1|LessThan1~533 divide:u1|LessThan1~536 divide:u1|LessThan1~538 divide:u1|LessThan1~542 divide:u1|p1~537 divide:u1|p1~532 divide:u1|c1~374 divide:u1|c1[5] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "24.900 ns" { divide:u1|c1[18] {} divide:u1|LessThan1~533 {} divide:u1|LessThan1~536 {} divide:u1|LessThan1~538 {} divide:u1|LessThan1~542 {} divide:u1|p1~537 {} divide:u1|p1~532 {} divide:u1|c1~374 {} divide:u1|c1[5] {} } { 0.000ns 2.800ns 0.600ns 0.600ns 0.600ns 2.200ns 0.000ns 0.600ns 2.600ns } { 0.000ns 2.300ns 1.800ns 1.800ns 2.300ns 1.200ns 1.500ns 2.300ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 10.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk0\" to destination register is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk0 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.000 ns) + CELL(0.000 ns) 10.500 ns divide:u1\|c1\[5\] 2 REG LC2_A18 5 " "Info: 2: + IC(7.000 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC2_A18; Fanout = 5; REG Node = 'divide:u1\|c1\[5\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk0 divide:u1|c1[5] } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 33.33 % ) " "Info: Total cell delay = 3.500 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 66.67 % ) " "Info: Total interconnect delay = 7.000 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk0 divide:u1|c1[5] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk0 {} clk0~out {} divide:u1|c1[5] {} } { 0.000ns 0.000ns 7.000ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 10.500 ns - Longest register " "Info: - Longest clock path from clock \"clk0\" to source register is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk0 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.000 ns) + CELL(0.000 ns) 10.500 ns divide:u1\|c1\[18\] 2 REG LC8_A19 7 " "Info: 2: + IC(7.000 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC8_A19; Fanout = 7; REG Node = 'divide:u1\|c1\[18\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk0 divide:u1|c1[18] } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 33.33 % ) " "Info: Total cell delay = 3.500 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 66.67 % ) " "Info: Total interconnect delay = 7.000 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk0 divide:u1|c1[18] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk0 {} clk0~out {} divide:u1|c1[18] {} } { 0.000ns 0.000ns 7.000ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk0 divide:u1|c1[5] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk0 {} clk0~out {} divide:u1|c1[5] {} } { 0.000ns 0.000ns 7.000ns } { 0.000ns 3.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk0 divide:u1|c1[18] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk0 {} clk0~out {} divide:u1|c1[18] {} } { 0.000ns 0.000ns 7.000ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "24.900 ns" { divide:u1|c1[18] divide:u1|LessThan1~533 divide:u1|LessThan1~536 divide:u1|LessThan1~538 divide:u1|LessThan1~542 divide:u1|p1~537 divide:u1|p1~532 divide:u1|c1~374 divide:u1|c1[5] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "24.900 ns" { divide:u1|c1[18] {} divide:u1|LessThan1~533 {} divide:u1|LessThan1~536 {} divide:u1|LessThan1~538 {} divide:u1|LessThan1~542 {} divide:u1|p1~537 {} divide:u1|p1~532 {} divide:u1|c1~374 {} divide:u1|c1[5] {} } { 0.000ns 2.800ns 0.600ns 0.600ns 0.600ns 2.200ns 0.000ns 0.600ns 2.600ns } { 0.000ns 2.300ns 1.800ns 1.800ns 2.300ns 1.200ns 1.500ns 2.300ns 1.700ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk0 divide:u1|c1[5] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk0 {} clk0~out {} divide:u1|c1[5] {} } { 0.000ns 0.000ns 7.000ns } { 0.000ns 3.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk0 divide:u1|c1[18] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk0 {} clk0~out {} divide:u1|c1[18] {} } { 0.000ns 0.000ns 7.000ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk1 register register led:u3\|a\[1\] led:u3\|a\[1\] 125.0 MHz Internal " "Info: Clock \"clk1\" Internal fmax is restricted to 125.0 MHz between source register \"led:u3\|a\[1\]\" and destination register \"led:u3\|a\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register register " "Info: + Longest register to register delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:u3\|a\[1\] 1 REG LC3_C8 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C8; Fanout = 15; REG Node = 'led:u3\|a\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:u3|a[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 2.300 ns led:u3\|a\[1\] 2 REG LC3_C8 15 " "Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC3_C8; Fanout = 15; REG Node = 'led:u3\|a\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { led:u3|a[1] led:u3|a[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns ( 73.91 % ) " "Info: Total cell delay = 1.700 ns ( 73.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.09 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { led:u3|a[1] led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { led:u3|a[1] {} led:u3|a[1] {} } { 0.000ns 0.600ns } { 0.000ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 6.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_28 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_28; Fanout = 3; CLK Node = 'clk1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.000 ns) 6.200 ns led:u3\|a\[1\] 2 REG LC3_C8 15 " "Info: 2: + IC(2.700 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = LC3_C8; Fanout = 15; REG Node = 'led:u3\|a\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk1 led:u3|a[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 56.45 % ) " "Info: Total cell delay = 3.500 ns ( 56.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 43.55 % ) " "Info: Total interconnect delay = 2.700 ns ( 43.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { clk1 led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.200 ns" { clk1 {} clk1~out {} led:u3|a[1] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 6.200 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_28 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_28; Fanout = 3; CLK Node = 'clk1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.000 ns) 6.200 ns led:u3\|a\[1\] 2 REG LC3_C8 15 " "Info: 2: + IC(2.700 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = LC3_C8; Fanout = 15; REG Node = 'led:u3\|a\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk1 led:u3|a[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 56.45 % ) " "Info: Total cell delay = 3.500 ns ( 56.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 43.55 % ) " "Info: Total interconnect delay = 2.700 ns ( 43.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { clk1 led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.200 ns" { clk1 {} clk1~out {} led:u3|a[1] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { clk1 led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.200 ns" { clk1 {} clk1~out {} led:u3|a[1] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } "" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.200 ns" { clk1 {} clk1~out {} led:u3|a[1] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { led:u3|a[1] led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { led:u3|a[1] {} led:u3|a[1] {} } { 0.000ns 0.600ns } { 0.000ns 1.700ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { clk1 led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.200 ns" { clk1 {} clk1~out {} led:u3|a[1] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } "" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.200 ns" { clk1 {} clk1~out {} led:u3|a[1] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:u3|a[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "" { led:u3|a[1] {} } {  } {  } "" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 30 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk0 150 " "Warning: Circuit may not operate. Detected 150 non-operational path(s) clocked by clock \"clk0\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}