time.map.summary

用VHDL开发的数字钟资料 完整的实验代码

Analysis & Synthesis Status : Successful - Wed Apr 22 22:11:30 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : time
Top-level Entity Name : time
Family : FLEX10K
Total logic elements : 75
Total pins : 27
Total memory bits : 0