vhdl1.vhd

基于vhdl的数字钟完整工程文件

-- 2/3/4/10jishu
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
 port (clk :in std_logic;
        rst :in std_logic;
        en :in std_logic;
        mset : in std_logic_vector(1 downto 0);
        yout : out std_logic_vector(3 downto 0);
        cout: out std_logic);
end count;
architecture behav of count is
signal cq1:std_logic_vector(3 downto 0);
signal smod:std_logic_vector(3 downto 0);
begin
smod<="0001" when mset="01" else
      "0011" when mset="10" else
      "0010" when mset="00" else
      "1001";
p_reg:process(clk,rst,en)
 begin
  if rst='1' then cq1<=(others=>'0');
  elsif clk'event and clk='1' then
   if en='1' then
     if cq1<smod then cq1<=cq1+1;
      else cq1<=(others=>'0');
     end if;
   end if;
  end if;
yout<=cq1;
end process p_reg;
cout<=(cq1(0) xnor smod(0)) and (cq1(1) xnor smod(1)) and (cq1(2) xnor smod(2)) and (cq1(3) xnor smod(3));
end behav;
--jishitiaojie 
library ieee;
use ieee.std_logic_1164.all;
entity s_machine is 
port (funct: in std_logic;
      set :in std_logic;
      q_en : out std_logic_vector(3 downto 0));
end s_machine;
architecture behav of s_machine is
 type fsm_st is (s0,s1,s2,s3,s4);
 signal current_state,next_state,last_state:fsm_st:=s0;
 begin
reg:process(funct)
 begin
 if funct'event and funct='1'   then last_state<=current_state;
  current_state<=next_state;
 end if;
end process reg;
com:process(current_state)
begin
case current_state is
 when s0=>next_state<=s1;q_en<="0000";
when s1=>next_state<=s2;q_en<="0001";
when s2=>next_state<=s3;q_en<="0010";
when s3=>next_state<=s4;q_en<="0100";
when s4=>next_state<=s0;q_en<="1111";
end case;
end process;
end behav;
--shifenpinyuzhi
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity freq_d10 is
 port(clkf :in std_logic;
      en,set :in std_logic;
      outf:out std_logic);
end freq_d10;
architecture behav of freq_d10 is
signal cntout,cntout5,setclk :std_logic;
signal cq1,cq15 :std_logic_vector(3 downto 0);
begin
process(clkf)
begin
if clkf'event and clkf='1' then
if cq1<"1001" then cq1<=cq1+1;
else cq1<=(others=>'0');
end if;
end if;
end process;
cntout<='1' when cq1="0000" 
else '0';
outf<=clkf when (en='1') and (set='1') 
else set when en='1'
else cntout when (en='0') 
else '0';
end behav;
--dingchen
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;