plj.fit.summary

来自「基于vhdl 的数字频率计的设计源程序及工程文件」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Wed May 20 23:29:24 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : plj
Top-level Entity Name : plj
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Total logic elements : 251 / 4,992 ( 5 % )
Total pins : 12 / 147 ( 8 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0