prev_cmp_plj.qmsg

基于vhdl 的数字频率计的设计源程序及工程文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 12 14:49:22 2007 " "Info: Processing started: Wed Dec 12 14:49:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off plj -c plj " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off plj -c plj" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "plj.vhd 12 6 " "Info: Found 12 design units, including 6 entities, in source file plj.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen-rtl " "Info: Found design unit 1: fen-rtl" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 pilvji-rtl " "Info: Found design unit 2: pilvji-rtl" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 46 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 lock-rtl " "Info: Found design unit 3: lock-rtl" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 108 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sel-rtl " "Info: Found design unit 4: sel-rtl" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 127 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 ch-rtl " "Info: Found design unit 5: ch-rtl" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 147 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 plj-rtl " "Info: Found design unit 6: plj-rtl" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 172 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fen " "Info: Found entity 1: fen" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 pilvji " "Info: Found entity 2: pilvji" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 41 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 lock " "Info: Found entity 3: lock" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 103 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 sel " "Info: Found entity 4: sel" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 123 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 ch " "Info: Found entity 5: ch" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 141 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "6 plj " "Info: Found entity 6: plj" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 165 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "dian plj.vhd(152) " "Error (10482): VHDL error at plj.vhd(152): object \"dian\" is used but not declared" {  } { { "plj.vhd" "" { Text "D:/plj6/plj.vhd" 152 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Dec 12 14:49:25 2007 " "Error: Processing ended: Wed Dec 12 14:49:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 1  0 s " "Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}