plj.tan.summary

基于vhdl 的数字频率计的设计源程序及工程文件

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.100 ns
From           : clr
To             : pilvji:u2|alm
From Clock     : --
To Clock       : sig
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 27.200 ns
From           : ch:u4|tmp[1]
To             : temp[1]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.500 ns
From           : clr
To             : pilvji:u2|alm
From Clock     : --
To Clock       : sig
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 25.64 MHz ( period = 39.000 ns )
From           : lock:u3|m5[1]
To             : ch:u4|nod
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'sig'
Slack          : N/A
Required Time  : None
Actual Time    : 35.09 MHz ( period = 28.500 ns )
From           : pilvji:u2|c1[2]
To             : pilvji:u2|q1[3]
From Clock     : sig
To Clock       : sig
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ch:u4|sel[2]
To             : ch:u4|tmp[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 4

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 4

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