voltage_measure.vhd

利用CPLD对输入信号测量幅度

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;

entity voltage_measure is 
	port(clk :in std_logic;
		rst:in std_logic;
		dat_input :in std_logic_vector(7 downto 0);	--数据输入
		cat_choice : out std_logic_vector(5 downto 0);		--数码管选择
		segout : out std_logic_vector(6 downto 0);	--7段BCD
		decimal :out std_logic				--小数点
		);
	end voltage_measure;
	
architecture behave of voltage_measure is
	signal clk_scan:std_logic;
	signal dat: std_logic_vector(7 downto 0);	--数据输入
	signal cat : std_logic_vector(5 downto 0);  --选择6个数码管
	signal t_segout : std_logic_vector(6 downto 0);  --7段数码管
	signal t_decimal: std_logic;
	signal count1:integer range 0 to 49999;
	signal circle:integer range 0 to 5;
	signal num,num1,num2,num3,num4,num5,num6:integer range 0 to 9;	----修改
	
	
begin 
		--分频 to 0.5kHz--
process(clk)
	begin 
	if clk'event and clk='1' then 
		if count1=49999 then
			count1<=0;
			clk_scan<=not clk_scan;
		else count1<=count1+1;
		end if;
	end if;
end process;
	dat<=dat_input;

process(clk_scan,rst)
	variable a,b,c,d,e,f:integer;	
	
begin
	
if rst='1' then
	num1<=0;
	num2<=0;
	num3<=0;
	num4<=0;
	num5<=0;
	num6<=0;
end if;	
		
		--算法--修改--
		--0.01294 11	1
		--0.02588 2 	2
		--0.05176 47	4
		--0.10352 94	8
		--0.20705 88	16
		--0.41411 76	32
		--0.82823 52	64
		--1.65647 05	128
		
		
	a:=conv_integer(dat(0))*4+conv_integer(dat(1))*8+conv_integer(dat(2))*6+conv_integer(dat(3))*3
			+conv_integer(dat(4))*6+conv_integer(dat(5))*2+conv_integer(dat(6))*3+conv_integer(dat(7))*7;
		num1<=a-a/10*10;
	b:=conv_integer(dat(0))*9+conv_integer(dat(1))*8+conv_integer(dat(2))*7+conv_integer(dat(3))*5
			+conv_integer(dat(5))*1+conv_integer(dat(6))*2+conv_integer(dat(7))*4+a/10;
		num2<=b-b/10*10;
	c:=conv_integer(dat(0))*2+conv_integer(dat(1))*5+conv_integer(dat(2))+conv_integer(dat(3))*3
			+conv_integer(dat(4))*7+conv_integer(dat(5))*4+conv_integer(dat(6))*8+conv_integer(dat(7))*6+b/10;
		num3<=c-c/10*10;
	d:=conv_integer(dat(0))+conv_integer(dat(1))*2+conv_integer(dat(2))*5+conv_integer(dat(5))*1
			+conv_integer(dat(6))*2+conv_integer(dat(7))*5+c/10;
		num4<=d-d/10*10;
	e:=conv_integer(dat(3))+conv_integer(dat(4))*2+conv_integer(dat(5))*4+conv_integer(dat(6))*8+conv_integer(dat(7))*6+d/10;
		num5<=e-e/10*10;
	f:=conv_integer(dat(7))+e/10;
		num6<=f-f/10;
		
	-------------------------------------------------------------------------------------------------------------------------
	
	if(clk_scan'event and clk_scan='1')then
			if circle=5 then 
				circle<=0;
			else circle<=circle+1;
			end if;
		----------------模板----------修改-----------小数点还没有处理好!
			case circle is			
				when 0 =>cat<="011111";num<=num6;t_decimal<='0';			--第一位disp5数码管显示---最高位---cat0---pin63
		        when 1 =>cat<="101111";num<=num5;t_decimal<='1';			--第二位disp4数码管显示 		---cat5---pin70
	            when 2 =>cat<="110111";num<=num4;t_decimal<='0';			--第三位disp3数码管显示---		---cat4---pin69
	            when 3 =>cat<="111011";num<=num3;t_decimal<='0';			--第四位disp2数码管显示
	            when 4 =>cat<="111101";num<=num2;t_decimal<='0';			--第五位disp1数码管显示
		        when 5 =>cat<="111110";num<=num1;t_decimal<='0';			--最低位	--第六位disp0数码管显示			-----------cat1---pin66
			    when others  =>cat<="111111";
			end case;
		--------------------------------------------------------------
			case num is
				when 0 =>t_segout<="0111111";		--gfedcba
				when 1 =>t_segout<="0000110";
				when 2 =>t_segout<="1011011";
				when 3 =>t_segout<="1001111";
				when 4 =>t_segout<="1100110";
				when 5 =>t_segout<="1101101";
				when 6 =>t_segout<="1111101";
				when 7 =>t_segout<="0000111";
				when 8 =>t_segout<="1111111";
				when 9 =>t_segout<="1101111";
				when others=>t_segout<="0000000";
			end case;
	end if;
	segout<=t_segout;
	cat_choice<=cat;
	decimal<=t_decimal;
	end process;
end;