ram.sim.rpt

ram的vhdl源代码在colloy实现

+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      53.57 % ;
; Total nodes checked                                 ; 63           ;
; Total output ports checked                          ; 84           ;
; Total output ports with complete 1/0-value coverage ; 45           ;
; Total output ports with no 1/0-value coverage       ; 37           ;
; Total output ports with no 1-value coverage         ; 38           ;
; Total output ports with no 0-value coverage         ; 38           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                        ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |ram|add:inst2|a[1]    ; |ram|add:inst2|a[1]    ; regout           ;
; |ram|add:inst2|a[2]    ; |ram|add:inst2|a[2]    ; regout           ;
; |ram|add:inst2|a[3]    ; |ram|add:inst2|a[3]    ; regout           ;
; |ram|add:inst2|a[4]    ; |ram|add:inst2|a[4]    ; regout           ;
; |ram|add:inst2|a[1]~30 ; |ram|add:inst2|a[1]~30 ; combout          ;
; |ram|add:inst2|a[1]~30 ; |ram|add:inst2|a[1]~37 ; cout             ;
; |ram|add:inst2|a[2]~31 ; |ram|add:inst2|a[2]~31 ; combout          ;
; |ram|add:inst2|a[2]~31 ; |ram|add:inst2|a[2]~38 ; cout             ;
; |ram|add:inst2|a[3]~32 ; |ram|add:inst2|a[3]~32 ; combout          ;
; |ram|add:inst2|a[3]~32 ; |ram|add:inst2|a[3]~39 ; cout             ;
; |ram|add:inst2|a[4]~33 ; |ram|add:inst2|a[4]~33 ; combout          ;
; |ram|add:inst2|a[4]~33 ; |ram|add:inst2|a[4]~40 ; cout             ;
; |ram|add:inst2|a[5]~34 ; |ram|add:inst2|a[5]~34 ; combout          ;
; |ram|add:inst2|a[5]~34 ; |ram|add:inst2|a[5]~41 ; cout             ;
; |ram|add:inst2|a[6]~35 ; |ram|add:inst2|a[6]~35 ; combout          ;
; |ram|add:inst2|a[0]    ; |ram|add:inst2|a[0]    ; regout           ;
; |ram|add:inst2|a[0]~44 ; |ram|add:inst2|a[0]~44 ; combout          ;
; |ram|wr                ; |ram|wr                ; combout          ;
; |ram|out_clk           ; |ram|out_clk           ; combout          ;
; |ram|in_clk            ; |ram|in_clk            ; combout          ;
; |ram|data[15]          ; |ram|data[15]          ; combout          ;
; |ram|addr[0]           ; |ram|addr[0]           ; combout          ;
; |ram|addr[1]           ; |ram|addr[1]           ; combout          ;
; |ram|addr[2]           ; |ram|addr[2]           ; combout          ;
; |ram|addr[3]           ; |ram|addr[3]           ; combout          ;
; |ram|addr[4]           ; |ram|addr[4]           ; combout          ;
; |ram|addr[5]           ; |ram|addr[5]           ; combout          ;
; |ram|addr[6]           ; |ram|addr[6]           ; combout          ;
; |ram|addr[7]           ; |ram|addr[7]           ; combout          ;
; |ram|data[14]          ; |ram|data[14]          ; combout          ;
; |ram|data[13]          ; |ram|data[13]          ; combout          ;
; |ram|data[12]          ; |ram|data[12]          ; combout          ;
; |ram|data[11]          ; |ram|data[11]          ; combout          ;
; |ram|data[10]          ; |ram|data[10]          ; combout          ;
; |ram|data[9]           ; |ram|data[9]           ; combout          ;
; |ram|data[8]           ; |ram|data[8]           ; combout          ;
; |ram|data[7]           ; |ram|data[7]           ; combout          ;
; |ram|data[6]           ; |ram|data[6]           ; combout          ;
; |ram|data[5]           ; |ram|data[5]           ; combout          ;
; |ram|data[4]           ; |ram|data[4]           ; combout          ;
; |ram|data[3]           ; |ram|data[3]           ; combout          ;
; |ram|data[2]           ; |ram|data[2]           ; combout          ;
; |ram|data[1]           ; |ram|data[1]           ; combout          ;
; |ram|data[0]           ; |ram|data[0]           ; combout          ;
; |ram|out_clk~clkctrl   ; |ram|out_clk~clkctrl   ; outclk           ;
+------------------------+------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                                          ;
+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                ; Output Port Name                                                                                                    ; Output Port Type ;
+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+------------------+
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[0]  ; portadataout0    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[1]  ; portadataout1    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[2]  ; portadataout2    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[3]  ; portadataout3    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[4]  ; portadataout4    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[5]  ; portadataout5    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[6]  ; portadataout6    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[7]  ; portadataout7    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[8]  ; portadataout8    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[9]  ; portadataout9    ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[10] ; portadataout10   ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[11] ; portadataout11   ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[12] ; portadataout12   ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[13] ; portadataout13   ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[14] ; portadataout14   ;
; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0 ; |ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[15] ; portadataout15   ;
; |ram|add:inst2|a[6]                                                                                                      ; |ram|add:inst2|a[6]                                                                                                 ; regout           ;
; |ram|add:inst2|a[7]                                                                                                      ; |ram|add:inst2|a[7]                                                                                                 ; regout           ;
; |ram|add:inst2|a[6]~35                                                                                                   ; |ram|add:inst2|a[6]~42                                                                                              ; cout             ;
; |ram|add:inst2|a[7]~36                                                                                                   ; |ram|add:inst2|a[7]~36                                                                                              ; combout          ;
; |ram|inst4                                                                                                               ; |ram|inst4                                                                                                          ; combout          ;
; |ram|q[15]                                                                                                               ; |ram|q[15]                                                                                                          ; padio            ;