ram.hif

ram的vhdl源代码在colloy实现

PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_qto1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|70|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|70|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|70|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
..|..|70|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|70|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|70|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|70|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
..|..|70|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
memory:inst|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_qto1
# storage
db|ram.(11).cnf
db|ram.(11).cnf
# case_insensitive
# source_file
db|altsyncram_qto1.tdf
18709084bad07ce1709fc6a5d81a2
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated
}
# end
# entity
altsyncram_m5s1
# storage
db|ram.(12).cnf
db|ram.(12).cnf
# case_insensitive
# source_file
db|altsyncram_m5s1.tdf
3a2b8cd7dbc7d5d3728f21d6b8e6e52
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# hierarchies {
memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1
}
# end
# entity
ram
# storage
db|ram.(1).cnf
db|ram.(1).cnf
# case_insensitive
# source_file
ram.bdf
a0dcf8ae1453a8f6cdad661c1d86ae5
24
# hierarchies {
|
}
# end
# entity
sld_signaltap
# storage
db|ram.(13).cnf
db|ram.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|70|quartus|libraries|megafunctions|sld_signaltap.vhd
dfe652acee26b72b2fda5892aa5e58e
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
671116800
PARAMETER_UNKNOWN
USR
sld_ip_version
5
PARAMETER_SIGNED_DEC
DEF
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
DEF
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
40
PARAMETER_UNKNOWN
USR
sld_trigger_bits
40
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
6
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
30820
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
26229
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
128
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
7
PARAMETER_UNKNOWN
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
136
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_ela_control
# storage
db|ram.(14).cnf
db|ram.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|70|quartus|libraries|megafunctions|sld_ela_control.vhd
a345f87dcbc417967dccb34f3232b9b0
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
40
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
enable_clk_edge_def
0
PARAMETER_SIGNED_DEC
USR
enable_async_glitch
0
PARAMETER_SIGNED_DEC
USR
enable_sync_normal
1
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
7
PARAMETER_SIGNED_DEC
USR
sample_depth
128
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
136
PARAMETER_SIGNED_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(acq_trigger_in)
39 downto 0
PARAMETER_STRING
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|ram.(15).cnf
db|ram.(15).cnf
# case_insensitive
# source_file
..|..|70|quartus|libraries|megafunctions|lpm_shiftreg.tdf
da15e606a442587da69cd6a7646c77c
6
# user_parameter {
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
load
-1
1
data9
-1
1
data8
-1
1
data7
-1
1
data6
-1
1
data5
-1
1
data4
-1
1
data3
-1
1
data2
-1
1
data15
-1
1
data14
-1
1
data13
-1
1
data12
-1
1
data11
-1
1
data10
-1
1
data1
-1
1
data0
-1
1
}
# include_file {
..|..|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
..|..|70|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
..|..|70|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
}
# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|ram.(16).cnf
db|ram.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|70|quartus|libraries|megafunctions|sld_ela_control.vhd
a345f87dcbc417967dccb34f3232b9b0
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
40
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
136
PARAMETER_SIGNED_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
39 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_ena)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|ram.(17).cnf
db|ram.(17).cnf
# case_insensitive
# source_file
..|..|70|quartus|libraries|megafunctions|lpm_shiftreg.tdf
da15e606a442587da69cd6a7646c77c
6
# user_parameter {
LPM_WIDTH
120
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q99
-1
3
q98
-1
3
q97
-1
3
q96
-1
3
q95
-1
3
q94
-1
3
q93
-1
3
q92
-1
3