ram.tan.rpt

来自「ram的vhdl源代码在colloy实现」· RPT 代码 · 共 180 行 · 第 1/5 页

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programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+---------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                                                                                                                                             ; To                                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.854 ns                                       ; addr[3]                                                                                                                                                                                                                                                          ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]                                                                                                 ; --                           ; out_clk                      ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 12.199 ns                                      ; memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[0]                                                                                                                                                    ; q[0]                                                                                                                                                 ; out_clk                      ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 3.116 ns                                       ; altera_internal_jtag~TDO                                                                                                                                                                                                                                         ; altera_reserved_tdo                                                                                                                                  ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.640 ns                                       ; altera_internal_jtag~TDIUTAP                                                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3]                                                                                      ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 121.09 MHz ( period = 8.258 ns )               ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]                                                                                                                                                                                                               ; sld_hub:sld_hub_inst|hub_tdo~reg0                                                                                                                    ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'out_clk'                      ; N/A   ; None          ; 161.55 MHz ( period = 6.190 ns )               ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; out_clk                      ; out_clk                      ; 0            ;
; Clock Setup: 'wr'                           ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg15                                                                                                                           ; memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a15~portb_memory_reg0               ; wr                           ; wr                           ; 0            ;
; Clock Setup: 'ce'                           ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg15                                                                                                                           ; memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a15~portb_memory_reg0               ; ce                           ; ce                           ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                                                                                                                                                                                                                                  ;                                                                                                                                                      ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;