ram.tan.summary

ram的vhdl源代码在colloy实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.854 ns
From           : addr[3]
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]
From Clock     : --
To Clock       : out_clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.199 ns
From           : memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|q_a[0]
To             : q[0]
From Clock     : out_clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.116 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.640 ns
From           : altera_internal_jtag~TDIUTAP
To             : sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 121.09 MHz ( period = 8.258 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]
To             : sld_hub:sld_hub_inst|hub_tdo~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'out_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 161.55 MHz ( period = 6.190 ns )
From           : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena
From Clock     : out_clk
To Clock       : out_clk
Failed Paths   : 0

Type           : Clock Setup: 'wr'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg15
To             : memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a15~portb_memory_reg0
From Clock     : wr
To Clock       : wr
Failed Paths   : 0

Type           : Clock Setup: 'ce'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg15
To             : memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a15~portb_memory_reg0
From Clock     : ce
To Clock       : ce
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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