ram.fit.smsg

ram的vhdl源代码在colloy实现

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Apr 21 08:50:08 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ram -c ram
Info: Selected device EP2C20Q240C8 for design "ram"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 3 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 81 of 81 atoms in partition Top
    Info: Previous placement does not exist for 787 of 787 atoms in partition sld_signaltap:auto_signaltap_0
    Info: Previous placement does not exist for 172 of 172 atoms in partition sld_hub:sld_hub_inst
Info: Detected 2 design partitions (excluding Top) used without floorplan location assignments.
    Info: Design partition sld_signaltap:auto_signaltap_0 has no floorplan location assignments
    Info: Design partition sld_hub:sld_hub_inst has no floorplan location assignments
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 4
    Info: Pin ~nCSO~ is reserved at location 5
    Info: Pin ~LVDS91p/nCEO~ is reserved at location 127
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 1 pins of 43 total pins
    Info: Pin addr[0] not assigned to an exact location on the device
Info: Automatically promoted node out_clk (placed in PIN 209 (CLK8, LVDSCLK4n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10
Info: Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node inst3 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|reset_all 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset
Info: Automatically promoted node sld_hub:sld_hub_inst|CLR_SIGNAL 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell
Info: Automatically promoted node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~404
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_shift_load
Info: Automatically promoted node sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2]
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|ela_status~133
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~114
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable~33
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|edq~89
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|trigger_out_mode_ff~7
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 7 total pin(s) used --  12 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 8 total pin(s) used --  12 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  18 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available
        Info: I/O bank number 5 does not use VREF pins and has 3.30V VCCIO pins. 9 total pin(s) used --  11 pins available
        Info: I/O bank number 6 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  10 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  16 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 16 total pin(s) used --  2 pins available
Warning: Ignored locations or region assignments to the following nodes