divide.v

It is n-bit sequential divider in verilog language

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 20 July 5.50 pm
// 
// Create Date:    11:13 AM 8/21/2007
// Design Name: 
// Module Name:    Divide_2 --
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: Latest
//
//////////////////////////////////////////////////////////////////////////////////

module divider(clk, reset, load, dividend, divisor, done, quotient);
    
	 parameter Widthdividend = 32, // dividend
              Widthdivisor  = 32, //divisor
				  WidthCount    = 6;  //From

	 /*parameter Widthdividend = 20, // dividend
              Widthdivisor  = 20, //divisor
				  WidthCount    = 5;  //From*/
				  
    input  clk;
    input  reset;
    input  load;
    input  [Widthdividend - 1 : 0] dividend; //[19:0]
	 input  [Widthdivisor - 1  : 0] divisor;  //[19:0]

	 output done;
	 output [Widthdivisor - 1 : 0]quotient; //[19:0]
	 
    reg    done;
	 reg    [Widthdivisor - 1 : 0]quotient; //[19:0]

	 //FSM states
	 
			  
	 parameter ST_Waitload = 0,
              ST_Shift    = 1,
				  ST_Subtract = 2,
				  ST_done     = 3;

	reg [2:0] CurrentState, NextState;
	reg [WidthCount -1 :0] CurrentCount, NextCount;
	reg shift, subtract, A_GE_B;

   reg    [(Widthdividend*2) - 1 - Widthdivisor: 0] RegA; //[40-1-20 : 0], [19:0]
	reg    [Widthdivisor - 1 : 0] RegQ;							 //[19:0]
	reg    [Widthdivisor - 1 : 0] RegB;						    //[19:0]
	
	reg [(Widthdividend*2) - Widthdivisor - 1 : 0] notRegB;        //[40-20-1 : 0], [19:0]
	reg [(Widthdividend*2) - Widthdivisor - 1 : 0] RegA_minus_RegB;//[40-20-1 : 0], [19:0]
	
	
	//----------------------------------------------------------------------------------------------------------
	
	//			FSM Controller with Integrated counter
	
	//----------------------------------------------------------------------------------------------------------
	
	always @ (load or A_GE_B or CurrentCount or CurrentState)
	
	begin: FSM_COMB
	
		shift     = 0;
		subtract  = 0;
		done      = 0;
		NextCount = CurrentCount;
		
		
		case (CurrentState)
		
				ST_Waitload: begin
									NextCount = Widthdivisor;
										if (load)
											begin
												shift = 1;
												NextState = ST_Shift;
											end
										
										else
											NextState = ST_Waitload;
											
								end
								 
				ST_Shift  : if (CurrentCount == 0)

									begin
											/*done = 1; (Incase of Subtract one, then we get the o/p in next clk
																hence no done here, we just move to the "done State*/
											NextState = ST_done;
											
											if (A_GE_B)
												subtract = 1;
									end
								
								else if (A_GE_B)
									begin
											subtract = 1;
											NextState = ST_Subtract;
									end
	
								else
									begin
											shift = 1;
											NextCount = CurrentCount - 1;
											NextState = ST_Shift;
									end									
	
				ST_Subtract  : begin
										shift = 1;
										
											if (CurrentCount == 0)
												NextState = ST_done;

											else
												begin
													NextCount = CurrentCount - 1;
													NextState = ST_Shift;
												end
									end
										
				ST_done      :		if (load)
											begin
												shift = 1;
												done  = 0;
												NextCount = Widthdivisor;
												NextState = ST_Shift;
											end
											
										else
											begin
													done = 1;
													NextState = ST_done;
											end
											
				default      : NextState = CurrentState;
				
		endcase
	end
	

//-----------------------------------------------------------

//		State Updates

//-----------------------------------------------------------
	
	always @(posedge clk)
	
		begin
		
			if (!reset)
				begin
					CurrentCount <= Widthdivisor-1;
					CurrentState <= ST_Waitload;
				end
				
			else
				begin
					CurrentState <= NextState;
					CurrentCount <= NextCount;
				end
		
		end
		
//-----------------------------------------------------------

//		Compare (RegA - RegB)

//-----------------------------------------------------------

	always @(RegA or RegB)
		
		begin
		
			notRegB = ~ RegB;
			{A_GE_B, RegA_minus_RegB} = RegA + notRegB + 1;

		end
		
//-----------------------------------------------------------

//Data Registers, sequential output

//-----------------------------------------------------------

	always @ (posedge clk)
	
		begin
		
			//Synchronous reset
			
			if (!reset)
				begin
					RegA 		<= 0;
					RegB 		<= 0;
					RegQ 		<= 0;
					quotient <= 0000;
				end

			else if (load)
				begin
					{RegA, RegQ} <= dividend[(Widthdividend - 1):0];
					if ((divisor[(Widthdivisor - 1):0]) == 0)
							RegB <= 1;
					else
							RegB <= divisor[(Widthdivisor - 1):0];
				end

			//Shift
			
			else if (shift)
				{RegA, RegQ} <= {RegA, RegQ} << 1;
				
				
			//Subtract
			
			else if (subtract)
			
				begin
					RegQ[0] <= A_GE_B;
					RegA    <= RegA_minus_RegB;
				end
				
			else if (done)
			   
				begin
					quotient  <= RegQ;
				end
				
		end			//End for always block

endmodule