fdivision.tan.summary

verilog hdl经典例程

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.375 ns
From           : RESET
To             : j[1]
From Clock     : --
To Clock       : F10M
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.980 ns
From           : F500K~reg0
To             : F500K
From Clock     : F10M
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.682 ns
From           : RESET
To             : F500K~reg0
From Clock     : --
To Clock       : F10M
Failed Paths   : 0

Type           : Clock Setup: 'F10M'
Slack          : N/A
Required Time  : None
Actual Time    : 495.54 MHz ( period = 2.018 ns )
From           : j[0]
To             : j[1]
From Clock     : F10M
To Clock       : F10M
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------